Automatic architecture refinement techniques for customizing processing elements

Proceedings - Design Automation Conference

Volumn , Issue , 2008, Pages 379-384

  Gorjiara, Bita ^a   Gajski, Daniel ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

ASIP; Datapath; GNR; High level synthesis; Nanocoded architectures; Netlist; No instruction set computer (NISC); Power; Refinement

Indexed keywords

ASIP; DATAPATH; GNR; HIGH-LEVEL SYNTHESIS; NANOCODED ARCHITECTURES; NETLIST; NO INSTRUCTION-SET COMPUTER (NISC); POWER; REFINEMENT;

COMPUTER AIDED DESIGN; DIGITAL INTEGRATED CIRCUITS; ENERGY CONSERVATION; ENERGY EFFICIENCY; INDUSTRIAL ENGINEERING; OPTIMIZATION; TRIMMING; VERY LONG INSTRUCTION WORD ARCHITECTURE;

ARCHITECTURE;

EID: 51549099847     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2008.4555847     Document Type: Conference Paper

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