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Volumn , Issue , 2008, Pages 516-521

Dose map and placement co-optimization for timing yield enhancement and leakage power reduction

Author keywords

Dose map; Leakage power reduction; Placement; Timing yield

Indexed keywords

DOSE MAP; LEAKAGE POWER; LEAKAGE POWER REDUCTION; PLACEMENT; TIMING YIELD;

EID: 51549086167     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2008.4555871     Document Type: Conference Paper
Times cited : (7)

References (14)
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  • 2
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    • Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage
    • S. Bhardwaj, Y. Cao and S. Vrudhula, "Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage," IEEE ASPDAC, 2006, pp. 953-958.
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  • 3
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    • Gate-length biasing for runtime-leakage control
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    • Gupta, P.1    Kahng, A.B.2    Sharma, P.3    Sylvester, D.4
  • 4
    • 51549094859 scopus 로고    scopus 로고
    • http://wps2a.semi.org/cms/groups/public/documents/members only/van_schoot_presentat ion.pdf.
  • 7
    • 25144496964 scopus 로고    scopus 로고
    • 65nm node gate pattern using attenuated phase shift mask with off-axis illumination and sub-resolution assist features
    • G. Zhang, M. Terry, S. O'Brien et al., "65nm node gate pattern using attenuated phase shift mask with off-axis illumination and sub-resolution assist features," Proc. SPIE Symp. on Optical Microlithography XVIII, vol. 5754, 2005, pp. 760-772.
    • (2005) Proc. SPIE Symp. on Optical Microlithography XVIII , vol.5754 , pp. 760-772
    • Zhang, G.1    Terry, M.2    O'Brien, S.3
  • 8
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    • N. Jeewakhan, N. Shamma, S.-J. Choi et al., "Application of dosemapper for 65-nm gate CD control: strategies and results," Proc. SPIE Symp. on Photomask Technology, vol. 6349, 2006, p. 63490G.
    • (2006) Proc. SPIE Symp. on Photomask Technology , vol.6349
    • Jeewakhan, N.1    Shamma, N.2    Choi, S.-J.3
  • 10
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    • http://www.asml.com/
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    • Fast and exact simultaneous gate and wire sizing by lagrangian relaxation
    • C.-P. Chen, C. C. N. Chu and D. F. Wong, "Fast and exact simultaneous gate and wire sizing by lagrangian relaxation," IEEE Trans. on CAD 18(7) (1999), pp. 1014-1025.
    • (1999) IEEE Trans. on CAD , vol.18 , Issue.7 , pp. 1014-1025
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.