A 10-bit binary-weighted DAC with digital background LMS calibration

2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

Volumn , Issue , 2007, Pages 352-355

  Shen, Ding Lan ^a   Lai, Yuan Chun ^a   Lee, Tai Cheng ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

Binary weighted DAC; LMS calibration

Indexed keywords

BINARY-WEIGHTED DAC; HIGH SPEEDS; LMS CALIBRATION; SOLID-STATE CIRCUITS CONFERENCE;

DIGITAL INTEGRATED CIRCUITS;

EID: 51349114636     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2007.4425703     Document Type: Conference Paper

References (5)

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3. 2," IEEE J. Solid-State Circuits, vol. 39, pp. 1064.1072, 2004.
4. H.-U. Post and K. Schoppe, "A 14 bit monolithic NMOS D/A converter," IEEE J. Solid-State Circuits, vol. SC-18, pp. 297-302, 1983.
5. T.-C. Lee and B. Razavi, "A 125-MHz mixed-signal echo canceller for gigabit ethernet on copper wire," IEEE J. Solid-State Circuits, vol. 36, pp. 366-373, Mar. 2001.