Modular code generation from triggered and timed block diagrams

Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS

Volumn , Issue , 2008, Pages 147-158

  Lublinerman, Roberto ^a   Tripakis, Stavros ^b  

^a The Pennsylvania State University   (United States)

^b CADENCE DESIGN SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER NETWORKS; CONCENTRATION (PROCESS); DYNAMICAL SYSTEMS; FINITE AUTOMATA; INFORMATION ANALYSIS; NETWORK COMPONENTS; SCHRODINGER EQUATION;

BLOCK DIAGRAMS; CODE GENERATIONS; EMBEDDED TECHNOLOGY; MACRO BLOCK;

GRAPHIC METHODS;

EID: 51249100059     PISSN: 15453421     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RTAS.2008.12     Document Type: Conference Paper

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