An efficient power reduction technique for flash ADC

Proceedings - 20th Anniversary IEEE International SOC Conference

Volumn , Issue , 2007, Pages 43-46

  Hwang, Yuh Shyan ^a   Lin, Jeen Fong ^a,b   Huang, Cheng Chung ^a   Chen, Jiann Jong ^a   Lee, Wen Ta ^a  

^a NATIONAL TAIPEI UNIVERSITY OF TECHNOLOGY   (Taiwan)

^b Taipei College of Maritime Technology   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POWER UTILIZATION; PROGRAMMABLE LOGIC CONTROLLERS; TIME MEASUREMENT;

FLASH-ADC; POWER REDUCTIONS;

MULTICARRIER MODULATION;

EID: 51049113583     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOCC.2007.4545422     Document Type: Conference Paper

References (8)

1. M. Choi and A. A. Abidi, "A 6-b 1.3-Gsample/s A/D converter in 0.35-μm CMOS," IEEE Journal of Solid-State Circuits, Vol. 36, No. 12, pp. 1847-1858, Dec. 2001.
2. P. C. S. Scholtens and M. Vertregt, "A 6-b 1.6-Gsample/s flash ADC in 0.18 μm CMOS using averaging termination," IEEE Journal of Solid-State Circuits, Vol. 37, No. 12, pp. 1599-1609, Dec. 2002.
3. K. Uyttenhove and M. S. J. Steyaert, "A 1.8-V 6-bit 1.3-GHz flash ADC in 0.25μm CMOS," IEEE Journal of Solid-State Circuits, Vol. 38, No. 7, pp. 1115-1122, July 2003.
4. J. Terada, Y. Matsuya, F. Morisawa, and Y. Kado, "8-mW, 1-V, 100-Msps, 6-bit A/D converter using a transconductance latched comparator," IEEE Asia Pacific Conference on ASIC, 2000, pp. 53-56.
5. S. Kim and M. Song, "An 8-bit 200MSPS CMOS A/D Converter for analog interface module of TFT-LCD driver," IEEE International Symposium on Circuits and Systems, 2001, pp. 528-531.
6. M. Hotta and T. Matsuura, "Key technologies for miniaturization and power reduction of analog-to-digital converters for video use," IEICE Transactions on Electronics, Vol. E89-C, No. 6, pp. 664-672, June 2006.
7. V. Srinivas, S. Pavan, A. Lachhwani, and N. Sasidhar," A distortion compensating flash analog-to-digital conversion technique," IEEE Journal of Solid-State Circuits, Vol. 41, No. 9, pp. 1959-1969, Sept. 2006.
8. Chia-Chun Tsai, Kai-Wei Hong, Yuh-Shyan Hwang, Wen-Ta Lee and Trong-Yen Lee, " New power saving design method for CMOS flash ADC," IEEE International Midwest Symposium on Circuits and Systems, 2004, pp. III-371-III-374.