Impact of process induced stresses and chip-packaging interaction on reliability of air-gap interconnects

2008 IEEE International Interconnect Technology Conference, IITC

Volumn , Issue , 2008, Pages 135-137

  Zhang, Xuefeng ^a   Ryu, Suk Kyu ^a   Huang, Rui ^a   Ho, Paul S ^a   Liu, Junjun ^b   Toma, Dorel ^b  

^a The University of Texas at Austin   (United States)

^b Tokyo Electron US Holdings   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; COMPUTER NETWORKS; COPPER; DELAMINATION; ELECTRONIC EQUIPMENT MANUFACTURE; FINITE ELEMENT METHOD; FLOW INTERACTIONS; GALLIUM ALLOYS; MECHANICAL STABILITY; RAPID THERMAL ANNEALING; RELIABILITY; RISK ASSESSMENT; STEEL SHEET; THREE DIMENSIONAL;

AIR GAPS; CHANNEL CRACKING;

ELECTRONICS PACKAGING;

EID: 50949111986     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2008.4546947     Document Type: Conference Paper

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