A Novel Hardware Architecture for Self-adaptive Systems

Proceedings - 2007 NASA/ESA Conference on Adaptive Hardware and Systems, AHS-2007

Volumn , Issue , 2007, Pages 92-99

  Casas, José Antonio ^a   Moreno, Juan Manuel ^a   Madrenas, Jordi ^a   Cabestany, Joan ^a  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

FAULT TOLERANCE; NASA;

FAULT-TOLERANCE CAPABILITY; HARDWARE ARCHITECTURE; NOVEL HARDWARE; PROGRAMMABLE ARCHITECTURES; REGULAR ARRAY; SCALABILITY ISSUE; SELF CONFIGURATION; SELF-ADAPTIVE SYSTEM;

ADAPTIVE SYSTEMS;

EID: 50949088395     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/AHS.2007.11     Document Type: Conference Paper

References (8)

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3. th International Conference, ICES 2005, pp 180-182
4. Dimitri V. Yatsenko: Automated placement and routing of cell matrix circuits, Utah state university Logan, Utah 2003, pp 10-16.
5. J. M. Moreno, E. Sanchez, and J. Cabestany, "An In-System Routing Strategy for Evolvable Hardware Programmable Platforms," in Proceedings of the Third NASA/DoD Workshop on Evolvable Hardware, IEEE Computer Society Press, 2001, pp. 157-166.
6. C.Y. Lee, "An Algorithm for Path Connections and Its Applications" IRE Transactions on Electronic Computers, vol EC-10, pp. 346-365, September 1961
7. Michael G. Wrighton, André M. DeHon, "Hardware-Assisted Simulated Annealing with Application for Fast FPGA Placement", International Symposium on Field-Programmable Gate Arrays (FPGA'03), Feb. 23-25, 2003
8. http://www.aether-ist.org