Design and optimization of the SOI field effect diode (FED) for ESD protection

Solid-State Electronics

Volumn 52, Issue 10, 2008, Pages 1482-1485

  Yang, Yang ^a   Salman, Akram A ^b   Ioannou, Dimitris E ^a   Beebe, Stephen G ^b  

^a GEORGE MASON UNIVERSITY   (United States)

^b ADVANCED MICRO DEVICES   (United States)

Author keywords

Electrostatic discharge protection, ESD; Field effect diode, FED; PNPN

Indexed keywords

CARRIER LIFETIME; COMPUTER SIMULATION; ELECTRIC BREAKDOWN; ELECTRIC CONDUCTIVITY; ELECTROSTATIC DEVICES; ELECTROSTATIC DISCHARGE; FIELD EMISSION DISPLAYS; IONIZATION OF GASES; NONMETALS; SILICON;

BREAK DOWN VOLTAGES; DESIGN AND OPTIMIZATION; DEVICE OPERATIONS; DOPING PROFILES; ELECTROSTATIC DISCHARGE PROTECTION, ESD; ESD-PROTECTION; FIELD EFFECT DIODE; FIELD EFFECT DIODE, FED; HIGH GATE VOLTAGE; NUMERICAL SIMULATIONS; PNPN; SILICON-ON -INSULATOR;

SEMICONDUCTING SILICON COMPOUNDS;

EID: 50849098483     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2008.06.033     Document Type: Article

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