An efficient hardware implementation of the Tate Pairing in characteristic three

3rd International Conference on Systems, ICONS 2008

Volumn , Issue , 2008, Pages 23-28

  Kömürcü, Giray ^a,b   Savas, Erkay ^c  

^a BOGAZICI UNIVERSITY   (Turkey)

^b SCIENTIFIC AND TECHNOLOGICAL RESEARCH COUNCIL OF TURKEY   (Turkey)

^c SABANCI UNIVERSITY   (Turkey)

Author keywords

Bilinear pairings; Characteristic three; FPGA implementation; Hardware accelerator; Tate Pairing

Indexed keywords

COMPUTER NETWORKS;

BILINEAR PAIRINGS; CHARACTERISTIC THREE; FPGA IMPLEMENTATION; HARDWARE ACCELERATOR; TATE PAIRING;

CRYPTOGRAPHY;

EID: 50649116562     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICONS.2008.27     Document Type: Conference Paper

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