Algorithmic factorisation for low power FPGA implementations through increased data locality

2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT

Volumn , Issue , 2008, Pages 271-274

  McKeown, S ^a   Woods, R ^a   McAllister, J ^a  

^a QUEEN'S UNIVERSITY BELFAST   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

CHLORINE COMPOUNDS; COMPUTER NETWORKS; CONFORMAL MAPPING; FAST FOURIER TRANSFORMS; INDUSTRIAL ENGINEERING; INTERCONNECTION NETWORKS; METAL DRAWING; RAILROAD TUNNELS; REDUCTION;

DATA LOCALITY; INTERNATIONAL SYMPOSIUM; VLSI DESIGNS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 50649084341     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VDAT.2008.4542465     Document Type: Conference Paper

References (18)

1. T. Tuan and S. Trimberger, "The Power of FPGA Architectures," Xcell Journal, pp. 12-15, Second Quarter 2007.
2. W. Nebel et al, "Early Power-Aware Design & Validation: Myth or Reality?," Pro.c DAC, San Diego, USA, 2007.
3. S. Gupta and J. Anderson, "Optimizing FPGA Power with ISE Design Tools," Xcell Journal, pp. 16-19, Second Quarter 2007.
4. M. Pedram and A. Abdollahi, "Low-Power RT-Level synthesis techniques: a tutorial," in IEE Proc. of Comp. and Dig. Tech.., vol. 152, pp. 333-343, May 2005.
5. S. Narendra, V. De, S. Borkar, D. Antoniadis and A. Chandrakasan, "Full-Chip Subthreshold Leakage Power Prediction and Reduction Techniques for Sub-0.18-μm CMOS," IEEE Journal of Solid-State Circuits, vol. 39, pp. 501-510, February 2004.
6. C. Edwards, "Feel the Burn," IET Electronics, vol 5, pp. 22-29, August/September 2007.
7. N. Jha, "Low-power system scheduling, synthesis and displays," in IEE Proc.Comp. and Dig. Tech., vol. 152, pp.344-352, May 2006.
8. L. Benini, A. Bogliolo and G. De Micheli, "A Survey of Design Techniques for System-Level Dynamic Power Management," IEEE Trans. on VLSI Systems, vol. 8, pp.299-316, June 2000.
9. Z. Wang, E. Hsing, M. Sha and Y. Wang, "Partitioning and Scheduling DSP Applications with Maximal Memory Access Hiding," EURASIP Journal on App. Sig. Proc., vol 2002, pp. 926-935, 2002.
10. S. McKeown, S. Fischaber, R. Woods, J. McAllister and E. Malins, "Low Power Optimisation of DSP Core Networks on FPGA for High End Signal Processing Systems," 9th Int'l Conf. on Mil. and Aero. Prog. Logic Dev., Washington D.C., USA, 2006.
11. K. Srinivasan, N. Telkar, V. Ramamurthi, K. S. Chatha, "System-level design techniques for throughput and power optimization of multiprocessor SoC architectures," in Proc. of IEEE Ann. Symp. on VLSI Emerg. Trends in VLSI Syst. Des., pp. 39-45, Feb. 2004.
12. S. Barua, R. K. Thulasiram, P. Thulasiraman, "Improving data locality in parallel fast Fourier transform algorithm for pricing financial derivatives", in Proc. 18th Int'l Para. and Dist. Proc. Symp., pp. 235-240, April 2004.
13. S. Y. Kung, "VLSI Array Processors," New Jersey, Prentice Hall, 1988.
14. H. P. Peixoto, M. F. Jacome, "Algorithm and architecture-level design space exploration using hierarchical data flows," in Proc. IEEE Int'l Conf. on Appl.-Spec. Syst., Arch. and Proc., pp. 272-282, 1997.
15. J. Cooley and J. Tukey, "An algorithm for the machine calculation of complex Fourier series," Mathematics of Computation, vol. 19, pp. 297-301, 1965.
16. H. S. Stone, "Parallel Processing with the Perfect Shuffle," Transactions on Computers, vol. C-20, pp. 153-161, February 1971.
17. W. Li and L. Wanhammar, "A pipeline FFT processor," IEEE Workshop on Signal Processing Systems, pp. 654-662, 1999.
18. C. Hui, T. J. Ding, J. McCanny and R. Woods, "A 64-Point Fourier Transform Chip for Video Motion Compression Using Phase Correlation," IEEE Journal of solid-state circuits, vol. 31, pp. 1751-1761, Nov. 1996.