Metal carbides for band-edge work function metal gate CMOS devices

IEEE Transactions on Electron Devices

Volumn 55, Issue 9, 2008, Pages 2469-2474

  Hwang, Wan Sik ^a,b   Chan, Daniel S H ^a   Cho, Byung Jin ^c  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^b SAMSUNG Electronics   (South Korea)

^c Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

CMOS devices; Equivalent oxide thickness (EOT); Flatband voltage; HfC; high dielectric; Metal carbide; Metal gate; MOS capacitor; TaC; Work function (WF)

Indexed keywords

WORK FUNCTION;

CMOS DEVICES; EQUIVALENT OXIDE THICKNESS (EOT); FLATBAND VOLTAGE; HFC; METAL CARBIDE; METAL GATE; MOS CAPACITOR; TAC; WORK FUNCTION (WF);

METALS;

EID: 50549097125     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2008.927946     Document Type: Article

References (17)

1. J. Chen, B. Maiti, D. Connelly, M. Mendicino, F. Huang, O. Adetutu, Y. Yu, D. Weddington, W. Wu, J. Candelaria, D. Dow, P. Tobin, and J. Mogab, "0.18 μm metal gate fully-depleted SOI MOSFETs," in VLSI Symp. Tech, Dig., 1999, pp. 25-96.
2. H. Shimada, I. Ohshima, T. Ushiki, S. Sugawa, and T. Ohmi, "Tantalum nitride metal gate FD-SOI CMOS FETs using low resistivity self-grown bcc-tantalum layer," IEEE Trans. Electron Devices, vol. 48, no. 8, pp. 1619-1626, Aug. 2001.
3. M. F. Wang, Y.-C. Kao, T.-Y. Huang, H.-C. Lin, and C.-Y Chang, "Thermal stability of PVD TiN gate and its impacts on characteristics of CMOS transistors," in Proc. Int. Symp. P2ID, 2001, pp. 36-39.
4. C. Ren, D. S. H. Chan, B. B. Faizhal, M.-F. Li, Y.-C. Yeo, A. D. Trigg, A. Agarwal, N. Balasubramanian, J. S. Pan, P. C. Lim, and D.-L. Kwong, "Lanthanide-incorporated metal nitrides with tunable work function and good thermal stability for NMOS devices," in VLSI Symp. Tech. Dig. 2005, pp. 42-43.
5. J. K. Schaeffer, C. Capasso, L. R. C. Fonseca, S. Samavedam, D. C. Gilmer, Y. Liang, S. Kalpat, B. Adetutu, H.-H. Tseng, Y. Shiho, A. Demkov, R. Hegde, W. J. Taylor, R. Gregory, J. Jiang, E. Luckowski, M. V. Raymond, K. Moore, D. Triyoso, D. Roan, B. E. White, Jr., and P. J. Tobin, "Challenges for the integration of metal gate electrodes," in IEDM Tech. Dig., 2005, pp. 287-290.
6. Y. T. Hou, F. Y. Yen, P. F. Hsu, V. S. Chang, P. S. Lim, C. L. Hung, L. G. Yao, J. C. Jiang, H. J. Lin, Y. Jin, S. M. Jang, H. J. Tao, S. C. Chan, and M. S. Liang, "High performance tantalum carbide metal gate stacks for nMOSFEET application," in IEDM Tech. Dig., 2005, pp. 31-34.
7. x)-modulated work function and improved thermal stability." in Proc. Int. Conf. Solid State Devices Mater., 2005, pp. 850-851.
8. x) metal gate electrode for NMOS device application," in VLSI Symp. Tech. Dig., 2007, pp. 156-157.
9. H. O. Pierson, Handbook of Refractory Carbides and Nitrides. Park Ridge, NJ: Noyes, 1996.
10. W. S. Hwang, J. Chen, W. J. Yoo, and V. Bliznetsov, "Investigation of etching properties of metal nitride-high-k gate stacks using inductively coupled plasma," J. Vac. Sci. Technol. A, vol. 23, no. 4, pp. 964-970, Jul. 2005.
11. 2)x(SiON 1-x in dilute HF," J. Vac. Sci. Technol. A, vol. 25, p. 1056, Jul./Aug. 2007.
12. 2 and high-k gate stack systems using terraced oxide structures," in Proc. 35th IEEE Semicond. Interf. Spec. Conf., San Diego, CA, 2004.
13. M. Y. Liao, Y. Gotoh, H. Tsuji, and J. Ishikawa, "Deposition of vanadium carbide thin films using compound target sputtering and their field emission," J. Vac. Sci. Technol. A, vol. 5, pp. 1379-1383, Sep. 2005.
14. T. B. Massalski, P. R. Subramanian, H. Okamoto, and I. T. Kacprzak, Binary Alloy Phase Diagrams, 2nd ed. Materials Park, OH: ASM Int., 1990.
15. H.-S. Jung, J.-H. Lee, S. K. Han, Y.-S. Kim, H. J. Lim, M. J. Kim, S. J. Doh, M. Y. Yu, N.-I. Lee, H.-L. Lee, T.-S. Jeon, H.-J. Cho, S. B. Kang, S. Y. Kim, I. S. Park, D. Kim, H. S. Baik, and Y. S. Chung, "A highly manufacturable MIPS (metal inserted poly-Si stack) technology with novel threshold voltage control," in VLSI Symp. Tech. Dig., 2005, pp. 232-233.
16. t tuning utilizing La, Sc, Er, and Sr doped HfSiON dielectrics," in VLSI Symp. Tech. Dig., 2007, pp. 68-69.
17. H.-C. Wen, S. C. Song, C. S. Park, C. Burham, G. Bersuker, K. Choi, M. A. Quevedo-Lopez, B. S. Ju, H. N. Alshareef, H. Niimi, H. B. Park, P. S. Lysaght, P. Majhi, B. H. Lee, and R. Jammy, "Gate first metal-aluminum-nitride PMOS electrodes for 32 nm low standby power applications," in VLSI Symp. Tech. Dig., 2007, pp. 160-161.