Rate-compatible array LDPC codes

IEEE International Symposium on Information Theory - Proceedings

Volumn , Issue , 2004, Pages 153-

  Dholakia, Ajay ^a   Ölçer, Sedat ^a  

^a IBM RESEARCH ZURICH   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

DECODER ARCHITECTURE; LOW-DENSITY PARITY-CHECK (LDPC); RATE-COMPATIBLE ARRAY (RCA);

BIT ERROR RATE; CONVOLUTIONAL CODES; DECODING; MATRIX ALGEBRA; PIERCING; TURBO CODES;

CODES (SYMBOLS);

EID: 5044249741     PISSN: 21578097     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. E. Eleftheriou and S. Ölçer, "Low-density parity-check codes for digital subscriber lines," Proc. ICC, New York, NY, pp. 1752-1757, May 2002.
2. J. Ha and S. McLaughlin, "Optimal puncturing distributions for rate-compatible low-density parity-check codes," Proc. ISIT, p. 233, Yokohama, Japan, 2003.
3. J. Li and K. R. Narayanan, "Rate-compatible low density parity check codes for capacity-approaching ARQ schemes in packet data communications," Proc. Intl. Conf. Commun., Internet, Info. Tech., St. Thomas, Virgin Islands, pp. 201-206, Nov. 2002.
4. S. Ölçer, "Decoder architecture for array-code-based LDPC codes," Proc. Globecom, San Francisco, CA, pp. 2046-2050, Dec. 2003.
5. R. Mantha and F. R. Kschischang, "A capacity-approaching hybrid ARQ scheme using turbo codes," Proc. Globecom, Rio de Janeiro, Brazil, pp. 2341-2345, 1999.