A study of sub-40nm FinFET BE-SONOS NAND flash

2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design, Proceedings, NVSMW/ICMTD

Volumn , Issue , 2008, Pages 115-116

  Hsu, Tzu Hsuan ^a,b   Lue, Hang Ting ^a   Peng, Wu Chin ^a   Tsai, Cheng Hung ^a   King, Ya Chin ^b   Wang, Szu Yu ^a   Wu, Ming Tsung ^a   Hong, Shih Ping ^a   Hsieh, Jung Yu ^a   Yang, Ling Wu ^a   Lian, Nan Tzu ^a   Yang, Tahone ^a   Chen, Kuang Chao ^a   Hsieh, Kuang Yeu ^a   Liu, Rich ^a   Lu, Chih Yuan ^a  

^a MACRONIX INTERNATIONAL CO LTD   (Taiwan)

^b NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CONCURRENCY CONTROL; DATA STORAGE EQUIPMENT; ELECTRIC CONDUCTIVITY; FINS (HEAT EXCHANGE); SEMICONDUCTOR MATERIALS; SEMICONDUCTOR STORAGE; TECHNOLOGY;

BODY-TIED; DATA-RETENTION; DISTRIBUTION CONTROL; FIELD-ENHANCEMENT; HOLE TUNNELING; INTERNATIONAL CONFERENCES; MEMORY TECHNOLOGY; NAND FLASH; NON-VOLATILE; SEMICONDUCTOR MEMORIES; SWITCHING MECHANISMS;

FIELD EFFECT TRANSISTORS;

EID: 50249183520     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NVSMW.2008.39     Document Type: Conference Paper

References (3)

1. H. T. Lue, et, al, IEDM Tech. Dig., 2005, pp.547-550.
2. T. H. Hsu, et, al, IEDM Tech. Dig., 2007, pp.913-916.
3. H. T. Lue, et, al, IEDM Tech. Dig., 2007, pp.161-164.