45nm SOI CMOS Technology with 3X hole mobility enhancement and Asymmetric transistor for high performance CPU application

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2007, Pages 1035-1037

  Fung, Samuel K H ^a   Lo, H C ^a   Cheng, C F ^a   Lu, W Y ^a   Wu, K C ^a   Chen, K H ^a   Lee, D H ^a   Liu, Y H ^a   Wu, I L ^a   Li, C T ^a   Wu, C H ^a   Hsiao, F L ^a   Chen, T L ^a   Lien, W Y ^a   Huang, C H ^a   Wang, P W ^a   Chiu, Y H ^a   Lin, L T ^a   Chen, K Y ^a   Tao, H J ^a   Tuan, H C ^a   Mii, Y J ^a   Sun, Y C ^a   more..

^a TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON DEVICES; HIGH PERFORMANCE LIQUID CHROMATOGRAPHY; MOSFET DEVICES; SILICON; TECHNOLOGY; THICK FILMS;

ACTIVE AREAS; HIGH DRIVE CURRENT; MOBILITY ENHANCEMENT; SOI CMOS; SOI TECHNOLOGY; THIN FILM SOI; VOLUME RATIOS;

HOLE MOBILITY;

EID: 50249129306     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2007.4418928     Document Type: Conference Paper

References (6)

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3. Z. Luo et al., VLSI Tech. Symp., p. 16, 2007
4. S. Thompson et al., IEDM 2006.
5. T. Ghani et al., VLSI 2001.
6. K.L.Cheng, et al., accepted in IEDM 2007.