Feasible integration scheme for dual work function FUSI/HfSiON gate stacks with selective metal pile-up to nMOSFET

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2007, Pages 519-522

  Tsuchiya, Yoshinori ^a   Yoshiki, Masahiko ^a   Kaneko, Akio ^a   Inumiya, Seiji ^a   Saito, Tomohiro ^a   Nakajima, Kazuaki ^a   Aoyama, Tomonori ^a   Koga, Junji ^a   Nishiyama, Akira ^a   Koyama, Masato ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DUAL WORK FUNCTION; GATE STACKS; INTEGRATION SCHEMES; LOW-WORK FUNCTIONS; N-MOSFET; PHASE CHANGE PROCESSES; PILE UPS;

ELECTRON DEVICES; METALS; NICKEL; PILES;

WORK FUNCTION;

EID: 50249124544     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2007.4418989     Document Type: Conference Paper

References (13)

1. A. Veloso et al., IEDM2004, p. 855.
2. J. Kedzierski et al., IEEE-TED 52, (2005) 39.
3. H. Y. Yu et al., VLSI2006, p.120.
4. Y. Tsuchiya et al., IEDM2006, p.231.
5. K. Takahashi et al., IEDM2004, p. 367.
6. H. Y. Yu et al., VLSI2007, p.18.
7. A. Lauwers et al, IEDM2005, p.661
8. A. Veloso et al., VLSI2006, p.116
9. Binary Alloy Phase Diagrams
10. H.B. Michaelson, JAP 48, (1977)4729.
11. A. Siokou et al., Sur. Sci. 331, (1995) 580.
12. Y. Tsuchiya et al., IEEE-TED 53 (2006)30.
13. th edition