A novel cell arrangement enabling Trench DRAM scaling to 40nm and beyond

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2007, Pages 31-34

  Heineck, L ^a   Graf, W ^a   Popp, M ^a   Savignac, D ^a   Moll, H P ^a   Tews, R ^a   Temmler, D ^a   Kar, G ^a   Schmid, J ^a   Rouhanian, M ^a   Uhlig, I ^a   Goldbach, M ^a   Landgraf, E ^a   Dreeskornfeld, L ^a   Drubba, M ^a   Lukas, S ^a   Weinmann, D ^a   Roesner, W ^a   Mueller, W ^a  

^a QIMONDA DRESDEN GMBH AND CO OHG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; DYNAMIC RANDOM ACCESS STORAGE; ELECTRIC CURRENTS; ELECTRON DEVICES;

CELL ARCHITECTURES; DRAM TECHNOLOGY; FULL INTEGRATION; INTERNAL VOLTAGE; KEY TECHNOLOGIES; PARASITIC CAPACITANCES; PRODUCT DATA; SELF-ALIGNMENT; WORD LINES;

TECHNOLOGY;

EID: 50249088094     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2007.4418855     Document Type: Conference Paper

References (5)

1. W. Mueller et al., "Challenges for the DRAM Scaling to 40nm", IEDM 2005.
2. J. Y. Kim et al., "The Breakthrough in Data Retention Time of DRAM using Recess-Channel-Array Transistor (RCAT) for 88nm Feature Size and Beyond", VLSI 2003.
3. J. Amon et al., " A Highly Manufacturable Deep Trench Based DRAM Cell Layout with a Planar Array Device in a 70nm Technology, " IEDM 2004.
4. T. Tran et al., " A 58nm Trench DRAM Technology", IEDM 2006.
5. G. Aichmayr et al., "Carbon/ high-k Trench DRAM Generation", VLSI 2007.