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Volumn , Issue , 2007, Pages 381-384

Exploiting slack time in dynamically reconfigurable processor architectures

Author keywords

[No Author keywords available]

Indexed keywords

TECHNOLOGY;

EID: 50149106088     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPT.2007.4439291     Document Type: Conference Paper
Times cited : (11)

References (12)
  • 1
    • 36348972210 scopus 로고
    • Alpha-power law mosfet model and its application to cmos inverter delay and other formulas
    • T. Sakurai and R. Newton, "Alpha-power law mosfet model and its application to cmos inverter delay and other formulas," IEEE JSSC, vol. 15, no. 5, pp. 584-594, 1990.
    • (1990) IEEE JSSC , vol.15 , Issue.5 , pp. 584-594
    • Sakurai, T.1    Newton, R.2
  • 2
    • 33845573958 scopus 로고    scopus 로고
    • A survey of dynamically reconfigurable processors
    • H. Amano, "A survey of dynamically reconfigurable processors," IEICE Transcations on Communications, vol. E89-B, no. 12, pp. 3179-3189, 2006.
    • (2006) IEICE Transcations on Communications , vol.E89-B , Issue.12 , pp. 3179-3189
    • Amano, H.1
  • 3
    • 0842329349 scopus 로고    scopus 로고
    • A dynamically reconfigurable processor architecture
    • M. Motomura, "A dynamically reconfigurable processor architecture," in Microprocessor Forum, 2002.
    • (2002) Microprocessor Forum
    • Motomura, M.1
  • 5
    • 33746898894 scopus 로고    scopus 로고
    • Evaluation of temporal-spatial voltage scaling for processor-like reconfigurable architectures
    • T. Schweizer, J. Oliveira Filho, T. Oppold, T. Kuhn, and W. Rosenstiel, "Evaluation of temporal-spatial voltage scaling for processor-like reconfigurable architectures," in Euro DesignCon, 2005.
    • (2005) Euro DesignCon
    • Schweizer, T.1    Oliveira Filho, J.2    Oppold, T.3    Kuhn, T.4    Rosenstiel, W.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.