-
1
-
-
36348972210
-
Alpha-power law mosfet model and its application to cmos inverter delay and other formulas
-
T. Sakurai and R. Newton, "Alpha-power law mosfet model and its application to cmos inverter delay and other formulas," IEEE JSSC, vol. 15, no. 5, pp. 584-594, 1990.
-
(1990)
IEEE JSSC
, vol.15
, Issue.5
, pp. 584-594
-
-
Sakurai, T.1
Newton, R.2
-
2
-
-
33845573958
-
A survey of dynamically reconfigurable processors
-
H. Amano, "A survey of dynamically reconfigurable processors," IEICE Transcations on Communications, vol. E89-B, no. 12, pp. 3179-3189, 2006.
-
(2006)
IEICE Transcations on Communications
, vol.E89-B
, Issue.12
, pp. 3179-3189
-
-
Amano, H.1
-
3
-
-
0842329349
-
A dynamically reconfigurable processor architecture
-
M. Motomura, "A dynamically reconfigurable processor architecture," in Microprocessor Forum, 2002.
-
(2002)
Microprocessor Forum
-
-
Motomura, M.1
-
4
-
-
46249084131
-
A context dependent clock control mechanism for dynamically reconfigurable processors
-
H. Amano, Y. Hasegawa, S. Abe, K. Ishikawa, S. Tsutumi, S. Kurotaki, T. Nakumura, and T. Nishimura, "A context dependent clock control mechanism for dynamically reconfigurable processors," in International Conference on Field Programmable Logic and Applications (FPL), 2006.
-
(2006)
International Conference on Field Programmable Logic and Applications (FPL)
-
-
Amano, H.1
Hasegawa, Y.2
Abe, S.3
Ishikawa, K.4
Tsutumi, S.5
Kurotaki, S.6
Nakumura, T.7
Nishimura, T.8
-
5
-
-
33746898894
-
Evaluation of temporal-spatial voltage scaling for processor-like reconfigurable architectures
-
T. Schweizer, J. Oliveira Filho, T. Oppold, T. Kuhn, and W. Rosenstiel, "Evaluation of temporal-spatial voltage scaling for processor-like reconfigurable architectures," in Euro DesignCon, 2005.
-
(2005)
Euro DesignCon
-
-
Schweizer, T.1
Oliveira Filho, J.2
Oppold, T.3
Kuhn, T.4
Rosenstiel, W.5
-
7
-
-
2442422090
-
Low-power FPGA using pre-defined dual-vdd/dual-vt fabrics
-
F. Li, Y. Lin, L. He, and J. Cong, "Low-power FPGA using pre-defined dual-vdd/dual-vt fabrics," in International Symposium Field-Programmable Gate Array (FPGA), 2004.
-
(2004)
International Symposium Field-Programmable Gate Array (FPGA)
-
-
Li, F.1
Lin, Y.2
He, L.3
Cong, J.4
-
9
-
-
4644316767
-
Synchroscalar: A multiple clock domain, power-aware, tile-based embedded processor
-
J. Oliver, R. Rao, P. Sultana, J. Crandall, E. Czernikowski, L. W. Jones, D. Franklin, V. Akella, and F. Chong, "Synchroscalar: a multiple clock domain, power-aware, tile-based embedded processor," in International Symposium on Computer Architecture, 2004.
-
(2004)
International Symposium on Computer Architecture
-
-
Oliver, J.1
Rao, R.2
Sultana, P.3
Crandall, J.4
Czernikowski, E.5
Jones, L.W.6
Franklin, D.7
Akella, V.8
Chong, F.9
-
10
-
-
33746881989
-
Cost functions for the design of dynamically reconfigurable processor architectures
-
T. Oppold, T. Schweizer, T. Kuhn, and W. Rosenstiel, "Cost functions for the design of dynamically reconfigurable processor architectures," in Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), 2004.
-
(2004)
Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI)
-
-
Oppold, T.1
Schweizer, T.2
Kuhn, T.3
Rosenstiel, W.4
-
11
-
-
17844363460
-
Architecture exploration for a reconfigurable architecture template
-
B. Mei, A. Lambrechts, D. Verkest, J.-Y. Mignolet, and R. Lauwereins, "Architecture exploration for a reconfigurable architecture template," IEEE Design & Test of Computers, vol. 22, no. 2, pp. 90-101, 2005.
-
(2005)
IEEE Design & Test of Computers
, vol.22
, Issue.2
, pp. 90-101
-
-
Mei, B.1
Lambrechts, A.2
Verkest, D.3
Mignolet, J.-Y.4
Lauwereins, R.5
-
12
-
-
46249104452
-
Execution schemes for dynamically reconfigurable architectures
-
T. Oppold, T. Schweizer, J. Oliveira Filho, S. Eisenhardt, T. Kuhn, and W. Rosenstiel, "Execution schemes for dynamically reconfigurable architectures," in Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), 2006.
-
(2006)
Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI)
-
-
Oppold, T.1
Schweizer, T.2
Oliveira Filho, J.3
Eisenhardt, S.4
Kuhn, T.5
Rosenstiel, W.6
|