An efficient H.264 intra frame coder system design

2007 IFIP International Conference on Very Large Scale Integration, VLSI-SoC

Volumn , Issue , 2007, Pages 200-205

  Hamzaoglu, Ilker ^a   Tasdizen, Ozgur ^a   Sahin, Esra ^a  

^a SABANCI UNIVERSITY   (Turkey)

Author keywords

[No Author keywords available]

Indexed keywords

CODES (STANDARDS); CODES (SYMBOLS); LSI CIRCUITS; PROGRAMMABLE LOGIC CONTROLLERS;

HARDWARE AND SOFTWARE; HARDWARE COSTS; HARDWARE DESIGNS; INTERNATIONAL CONFERENCES; INTRA PREDICTION; PLATFORM DEVELOPMENT; PORTABLE APPLICATIONS; POST-PROCESSING; PRE-PROCESSING; REAL-TIME PERFORMANCE; SYSTEM DESIGNS; VERILOG; VERILOG HDL; VERY LARGE-SCALE INTEGRATION; XILINX VIRTEX-II FPGA;

COMPUTER HARDWARE DESCRIPTION LANGUAGES;

EID: 50149092287     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSISOC.2007.4402498     Document Type: Conference Paper

References (8)

1. T. Wiegand, G. J. Sullivan, G. Bjontegaard, and A. Luthra, "Overview of the H.264/AVC Video Coding Standard", IEEE Trans. on Circuits and Systems for Video Technology, vol. 13, no. 7, pp. 560-576, July 2003.
2. I. G. Richardson, H.264 and MPEG-4 Video Compression, Wiley, 2003.
3. Joint Video Team (JVT) of ITU-T VCEG and ISO/WC MPEG, Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification, ITU-T Rec. H.264 and ISO/IEC 14496-10 AVC, May 2003.
4. Y. Huang, B. Hsieh, T. Chen, and L. Chen, "Hardware Architecture Design for H.264/AVC Intra Frame Coder", Proc. of WEE ISCAS, pp. 269-272, April 2004.
5. Y. Huang, B. Hsieh, T. Chen, and L. Chen, "Analysis, Fast Algorithm and VLSI Architecture Design for H.264/AVC Intra Frame Coder", IEEE Trans. on CAS for Video Technology, March 2005.
6. E. Sahin and I. Hamzaoglu, "An Efficient Hardware Architecture for H.264 Intra Prediction Algorithm", Design, Automation and Test in Europe (DATE) Conference, April 2007.
7. O. Tasdizen and I. Hamzaoglu, "A High Performance and Low Cost Hardware Architecture for H.264 Transform and Quantization Algorithms", European Signal Processing Conf., September 2005.
8. E. Sahin and I. Hamzaoglu, "A High Performance and Low Power Hardware Architecture for H.264 CAVLC Algorithm", European Signal Processing Conf., September 2005.