The evaluation of flip chip bumping on Cu/low-κ wafer

Proceedings of 4th Electronics Packaging Technology Conference, EPTC 2002

Volumn , Issue , 2002, Pages 266-269

  Uang, R H ^a   Chang, Shu Ming ^a   Chen, Yu Chih ^a   Hu, Hsu Tien ^a   Lin, Jyh Rong ^a   Chen, Kuo Chuan ^a   Hwang, Yu Jiau ^a  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CHEMICAL STABILITY; CHIP SCALE PACKAGES; COPPER; DIELECTRIC MATERIALS; ELECTRONICS PACKAGING; FAILURE (MECHANICAL); INTEGRATED CIRCUIT INTERCONNECTS; ORGANIC POLYMERS; QUALITY CONTROL; SEMICONDUCTOR DEVICES; SILICON OXIDES; SILICON WAFERS; STRESSES; TENSILE STRENGTH;

CU INTERCONNECTIONS; ELECTROLESS NICKEL; ELECTROPLATED COPPER; HIGH-SPEED DEVICES; MECHANICAL PERFORMANCE; SEMI-CONDUCTOR FABRICATION; SPIN ON DIELECTRICS; THERMAL DISSIPATION;

FLIP CHIP DEVICES;

EID: 50049091643     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPTC.2002.1185680     Document Type: Conference Paper

References (5)

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4. L. Mercado, C. Goldberg, and S.-M. Kuo, "A Simulation Method for Predicting Packaging Mechanical Reliability with Low-κ Dielectrics", IITC 2002
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