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Volumn 4875 LNCS, Issue , 2008, Pages 207-212

Minimizing the area for planar straight-line grid drawings

Author keywords

[No Author keywords available]

Indexed keywords

BOUNDED SIZE; EXPERIMENTAL STUDIES; GRAPH DRAWING; GRID DRAWINGS; INTERNATIONAL SYMPOSIUM; ITERATIVE APPROACHES; NP-COMPLETE; PLANAR GRAPHS; STRAIGHT-LINE DRAWINGS;

EID: 49949117182     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-77537-9_21     Document Type: Conference Paper
Times cited : (18)

References (6)
  • 1
    • 0002128850 scopus 로고
    • How to draw a planar graph on a grid
    • de Fraysseix, H., Pach, J., Pollack, R.: How to draw a planar graph on a grid. Combinatorica 10(1), 41-51 (1990)
    • (1990) Combinatorica , vol.10 , Issue.1 , pp. 41-51
    • de Fraysseix, H.1    Pach, J.2    Pollack, R.3
  • 4
    • 84915196973 scopus 로고
    • The NP-completeness of finding minimum area layouts for VLSI-circuits (to appear)
    • Technical Report RUU-CS-82-06, Institute of Information and Computing Sciences, Utrecht University
    • Kramer, M., van Leeuwen, J.: The NP-completeness of finding minimum area layouts for VLSI-circuits (to appear). Technical Report RUU-CS-82-06, Institute of Information and Computing Sciences, Utrecht University (1982)
    • (1982)
    • Kramer, M.1    van Leeuwen, J.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.