Fast speculative address generation and way caching for reducing L1 data cache energy

IEEE International Conference on Computer Design, ICCD 2006

Volumn , Issue , 2006, Pages 101-107

  Nicolaescu, Dan ^a   Salamat, Babak ^a   Veidenbaum, Alex ^a   Valero, Mateo ^b  

^a Ringgold Standard Institution Informatics   (United States)

^b UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

ADDRESS GENERATION; ASSOCIATIVITY; CACHE ACCESS LATENCY; CACHE ENERGY; CACHE ENERGY CONSUMPTION; COMPUTER DESIGNS; DATA CACHING; ENERGY CONSUMPTION; EXECUTION TIME; HIGH-PERFORMANCE PROCESSORS; INTERNATIONAL CONFERENCES; NEW APPROACHES; NEW PROCESSES; STATIC AND DYNAMIC; STATIC ENERGY;

CACHE MEMORY; ENERGY CONSERVATION; ENERGY POLICY; POWER GENERATION;

DATA REDUCTION;

EID: 49749137538     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2006.4380801     Document Type: Conference Paper

References (23)

1. G. Hinton and et al, "The microarchitecture of the Pentium 4 processor," Intel Technology Journal, vol. 4, 2001.
2. D. Boggs and et al, "The microarchitecture of the Intel Pentium4 processor on 90nm technology," Intel Technology Journal, Feb. 2004.
3. J. Davis and et al, "A 5.6GHz 64KB dual-read data cache for the POWER6 processor," in ISSCC, 2006.
4. S. Borkar, "Low power design challenges for the decade (invited talk)," in ASP-DAC, 2001.
5. K. Flautner and et al, "Drowsy caches: simple techniques for reducing leakage power," in ISCA, 2002.
6. D. Nicolaescu and et al, "Reducing power consumption for high-associativity data caches in embedded processors," in DATE, 2003.
7. R. Min, W.-B. Jone, and Y. Hu, "Location cache: a low-power 12 cache system," in ISLPED, 2004.
8. K. Inoue and K. Murakami, "Way-predicting set-associative cache for high performance and low energy consumption," in ISLPED, 1999.
9. C. McNairy and D. Soltis, "Itanium 2 processor microarchitecture, " IEEE Micro, vol. 23, no. 2, pp. 44-55, Mar./Apr. 2003.
10. MIPS R10000 Microprocessor User's Manual, MIPS Technologies, Inc., 1996, version 2.0.
11. R. E. Kessler, "The Alpha 21264 microprocessor," IEEE Micro, vol. 19, no. 2, pp. 24-36, Mar./Apr. 1999.
12. W. Tang and et al, "Simultaneous way-footprint prediction and branch prediction for energy savings in set-associative instruction caches," in WPMRT, 2001.
13. A. Veidenbaum and D. Nicolaescu, "Low energy, highly-associative cache design for embedded processors," in ICCD, 2004.
14. dd: A circuit technique to reduce leakage in deep-submicron cache memories," in ISLPED, 2000.
15. Y. Li and et al, "State-preserving vs. non-state-preserving leakage control in caches," in DATE, 2004.
16. S. Kaxiras and et al, "Cache decay: exploiting generational behavior to reduce cache leakage power," in ISCA, 2001.
17. E. S. Tam and et al, "Active management of data caches by exploiting reuse information," IEEE TC, vol. 48, no. 11, pp. 1244-1259, 1999.
18. S. Petit, J. Sahuquillo, J. M. Such, and D. Kaeli, "Exploiting temporal locality in drowsy cache policies," in CF, 2005.
19. E. Witchel and et al, "Direct addressed caches for reduced power consumption," in MICRO-34, 2001.
20. R. Gonzalez and et al, "A content aware integer register file organization," in ISCA, 2004.
21. D. Burger and T. M. Austin, "The SimpleScalar tool set," University of Wisconsin, Tech. Rep. TR-97-1342, 1997.
22. "Cacti4," http://quid.hpl.hp.com:9081/cacti/.
23. K. So and R. Rechtshaffen, "Cache operations by mru change," in ICCD, 1986.