Design flow for embedded FPGAs based on a flexible architecture template

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2008, Pages 56-61

  Neumann, B ^a   Von Sydow, T ^a   Blume, H ^a   Noll, T G ^a  

^a RWTH AACHEN UNIVERSITY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CANNING; CHLORINE COMPOUNDS; COMPUTATIONAL COMPLEXITY; DATA STORAGE EQUIPMENT; DIGITAL ARITHMETIC; DIGITAL SIGNAL PROCESSING; ELECTRIC POWER UTILIZATION; EMBEDDED SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FREQUENCY MULTIPLYING CIRCUITS; INDUSTRIAL ENGINEERING; PARALLEL PROCESSING SYSTEMS; PETROLEUM PRODUCTS; SIGNAL PROCESSING; STANDARDS; TESTING;

ALGORITHMIC COMPLEXITY; APPLICATION DOMAINS; CHIP AREAS; COMMERCIAL PRODUCTS; COMPUTATIONAL POWER; DESIGN FLOWS; DESIGN FRAMEWORK; DIGITAL SIGNAL PROCESSING APPLICATIONS; EMBEDDED FPGA; FLEXIBLE ARCHITECTURES; GENERAL-PURPOSE PROCESSOR; GENERAL-PURPOSE PROCESSORS; HIGH FLEXIBILITY; HIGH-LEVEL DESCRIPTIONS; LOW-POWER DISSIPATION; NET LIST; POWER DISSIPATIONS; PROCESSOR CORES; RE-CONFIGURABLE;

ARCHITECTURAL DESIGN;

EID: 49749134677     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2008.4484660     Document Type: Conference Paper

References (13)

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