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Volumn , Issue , 2008, Pages 1396-1401

Multicast parallel pipeline router architecture for Network-on-Chip

Author keywords

[No Author keywords available]

Indexed keywords

AREA OVERHEAD; COMMUNICATION LINK; DESTINATION NODES; MULTICAST; MULTICAST PACKETS; MULTICAST SERVICES; NETWORK ON CHIPS; NETWORK-ON-CHIP; ON-CHIP NETWORK; ROUTER ARCHITECTURES; UNICAST;

EID: 49749088882     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2008.4484869     Document Type: Conference Paper
Times cited : (49)

References (18)
  • 1
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  • 2
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    • Benini, L.1    De Micheli, G.2
  • 3
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    • Route Packets, Not Wires: On-Chip Interconnection Networks
    • W. J. Dally and B. Towles, "Route Packets, Not Wires: On-Chip Interconnection Networks," The 38th ACM Design Automation Conf., pp. 684-689, 2001.
    • (2001) The 38th ACM Design Automation Conf , pp. 684-689
    • Dally, W.J.1    Towles, B.2
  • 4
    • 0042111484 scopus 로고    scopus 로고
    • Kluwer Academic Publisher, Hingham, MA, USA
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    • (2003) Networks on Chip
    • Jantsch, A.1    Tenhunen, H.2
  • 6
    • 0036505033 scopus 로고    scopus 로고
    • The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs
    • Mar-Apr
    • M. B. Taylor, J. Kim, J. Miller, et. al., "The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs," IEEE Micro, vol. 22, issue 2, pp. 25-35, Mar-Apr. 2002.
    • (2002) IEEE Micro , vol.22 , Issue.2 , pp. 25-35
    • Taylor, M.B.1    Kim, J.2    Miller, J.3    et., al.4
  • 8
    • 0036760592 scopus 로고    scopus 로고
    • An Interconnect Architecture for Networking Systems on Chips
    • Sept-Oct
    • F. Karim, A. Nguyen and S. Dey, "An Interconnect Architecture for Networking Systems on Chips," IEEE Micro, vol. 22, issue 5, pp. 36-45, Sept-Oct. 2002.
    • (2002) IEEE Micro , vol.22 , Issue.5 , pp. 36-45
    • Karim, F.1    Nguyen, A.2    Dey, S.3
  • 12
    • 19344373694 scopus 로고    scopus 로고
    • Network-on-chip architectures and design methods
    • Mar
    • L. Benini and D. Bertozzi, "Network-on-chip architectures and design methods," IEE Proc. Computers and Digital Techniques, vol. 152, no.2, pp. 261-272, Mar. 2005.
    • (2005) IEE Proc. Computers and Digital Techniques , vol.152 , Issue.2 , pp. 261-272
    • Benini, L.1    Bertozzi, D.2
  • 14
    • 0036761283 scopus 로고    scopus 로고
    • Chain: A Delay-Insensitive Chip Area Interconnect
    • Sept-Oct
    • J. Bainbridge and S. Furber, "Chain: A Delay-Insensitive Chip Area Interconnect," IEEE Micro, vol. 22, issue 5, pp. 16-23, Sept-Oct. 2002.
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    • Bainbridge, J.1    Furber, S.2
  • 16
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    • Implementation of guaranteed services in the MANGO clockless network-on-chip
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    • T. Bjerregaard and J. Sparsø, "Implementation of guaranteed services in the MANGO clockless network-on-chip," IEE Proc. Computers and Digital Techniques, vol. 153, no.4, pp. 217-229, July 2006.
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    • Bjerregaard, T.1    Sparsø, J.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.