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Volumn 51, Issue , 2008, Pages 216-218

A 24GHz sub-harmonic receiver front-end with integrated multi-phase L0 generation in 65nm CMOS

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; SIGNAL PROCESSING;

EID: 49549106462     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2008.4523134     Document Type: Conference Paper
Times cited : (31)

References (3)


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.