Integrated offset trimming technique

European Solid-State Circuits Conference

Volumn , Issue , 2001, Pages 89-92

  Laville, S ^a   Pontarollo, S ^a   Dufaza, C ^b   Auvergne, D ^b  

^a STMICROELECTRONICS   (France)

^b LIRMM   (France)

Author keywords

[No Author keywords available]

Indexed keywords

BI-CMOS PROCESS; CIRCUIT ARCHITECTURES; CONTROL STRUCTURE; FULLY COMPATIBLE; OFFSET TRIMMINGS; PACKAGING TECHNIQUES; SNAP BACK; TRIMMING TECHNIQUES;

BICMOS TECHNOLOGY; TRIMMING;

ANALOG CIRCUITS;

EID: 49549097315     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. P.R. Gray and R.G. Meyer, "Analysis and Design of Analog Integrated Circuits", John Wiley & Sons, chapter 6, pp. 450-453, 1993.
2. K. Suzuki, "Internal Stress and Characteristic Shifts of Plastic Encapsulated Semiconductor Devices", Oyo Buturi, Vol. 48, pp. 1211, 1979.
3. S. Laville, C. Forel and S. Pontarollo, "Dispositif d'ajustement des circuits après mise en boîtier et procédé de fabrication correspondant", Patent no 9908240, June 1999.
4. A. Amerasckera, M-C. Chang, C. Duvvury and S. Ramaswamy, "Modeling MOS Snapback and Parasitic Bipolar Action for Circuit-Level-ESD and High-Current simulations", in Proc 34th IRPS, pp. 318-326, 1996.
5. P. Rossel, H. Tranduc and D. Montcoqut, "Avalanche Characteristic of MOS transistor", International Conference on Microelectronics, Vol 1, NIS, Yougoslavie, pp. 14-17, September 1997.
6. S. Laville, C. Forel, S. Pontarollo, C. Dufaza and D. Auvergne, "New Trimming Technique of Linear Analog Circuits with Programmable NMOS Snap Back", Proc. 15th DCIS-Design of Circuits and Integrated Systems Conference, Montpellier France, pp. 601-604, November. 2000.