A 45nm self-aligned-contact process 1Gb NOR flash with 5MB/s program speed

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 51, Issue , 2008, Pages 424-624

  Javanifard, Johnny ^a   Tanadi, Tris ^a   Giduturi, Hari ^a   Loe, Kim ^a   Melcher, Robert L ^a   Khabiri, Shahnam ^a   Hendrickson, Nicholas T ^a   Proescholdt, Andrew D ^a   Ward, David A ^a   Taylor, Mark A ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

SOLID STATE DEVICES;

DESIGN EFFORT; DESIGN RULES; DIE SIZE; NOR FLASH; PROGRAMMING PERFORMANCE; SELF ALIGNED CONTACTS; TECHNOLOGY NODES;

NETWORKS (CIRCUITS);

EID: 49549090473     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2008.4523238     Document Type: Conference Paper

References (5)

1. M. Taub, R. Bains, G. Barkley et al., "A 90nm 512Mb 166MHz Multilevel Cell Flash Memory with l.5MByte/s Programming," ISSCC Dig. Tech Papers, pp. 54-55, Feb. 2005.
2. D. Elmhurst, R. Bains, T. Bressie, et al., "A 1.8V 128Mb 125MHz Multilevel Cell Flash Memory with Flexible Read While Write," ISSCC Dig. Tech. Papers, pp. 286-287, Feb. 2003.
3. M. Yoshikawa, "Impact of Cell Threshold Voltage Distribution in the Array of Flash Memories on Scaled and Multilevel Flash Cell Design," Dig. Symp. VLSI Technology, pp. 240-241, Jun. 1995.
4. M. Bauer, R. Alexis, G. Atwood et al., "A Multilevel-Cell 32Mb Flash Memory," ISSCC Dig. Tech. Papers, pp. 132-133, Feb. 1995.
5. J.-D. Lee, S.-H. Hur and J.-D. Choi, "Effects of Floating-Gate Interference on NAND FlashCell Operation," Electron Device Letters, pp. 264-266, May 2002.