Threshold logic based adders using floating-gate circuits

Advances in Physics, Electronics and Signal Processing Applications

Volumn , Issue , 2000, Pages 54-58

  Rodriguez Villegas E ^a   Quintana, J M ^a   Avedillo, M J ^a   Rueda, A ^a  

^a Centro Informatico Cientifico de Andalucia   (Spain)

Author keywords

Arithmetic Circuits; Carry Lookahead Adders; Floating Gate Circuits; Threshold Logic

Indexed keywords

DELAY CIRCUITS; DIGITAL ARITHMETIC; GATES (TRANSISTOR); LOGIC CIRCUITS; MOS DEVICES; OPTIMIZATION; THRESHOLD LOGIC; TOPOLOGY;

ARITHMETIC CIRCUITS; CARRY LOOKAHEAD ADDERS; FLOATING-GATE CIRCUITS;

ADDERS;

EID: 4944254497     PISSN: None     EISSN: None     Source Type: Book    
DOI: None     Document Type: Article

References (4)

1. K. Hwang, Computer Arithmetic, Principles, Architecture and Design, John Wiley & Sons, 1979.
2. J.M. Quintana, "Arithmetic Operation with Threshold Logic", Internal Report, Institute de Microelectronica de Sevilla, IMSE-CNM, 1998.
3. T. Shibata and T. Ohmi, "A Functional MOS Transistor Featuring Gate Level Weighted Sum and Threshold Operations", IEEE Trans. on Electron Devices, 39, (6): 1444-1445, 1990.
4. M.J. Avedillo, J.M. Quintana, and A. Rueda, "Threshold Logic", Wiley Encyclopedia of Electrical and Electronics Engineering, (J.G. Webster, Ed.), Vol. 22, pp. 178-190.