Investigation of BPSG profile and FAB size on Cu stud bumping process by modeling and experiment

EuroSimE 2008 - International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Micro-Systems

Volumn , Issue , 2008, Pages

  Liu, Yumin ^a   Liu, Yong ^a   Scottirving, ^a   Luk, Timwah ^a   Wang, Qi ^a  

^a FAIRCHILD SEMICONDUCTOR   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONSUMER ELECTRONICS; COPPER; COPPER ALLOYS; ELECTRONICS INDUSTRY; EXPERIMENTS; GEOMORPHOLOGY; MICROELECTRONICS; NONMETALS; NONVOLATILE STORAGE; SEMICONDUCTING SILICON COMPOUNDS; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICES; SEMICONDUCTOR GROWTH; SHEARING; SILICON; SILICON WAFERS; SOLDERING; STRESSES; STUDS (FASTENERS); STUDS (STRUCTURAL MEMBERS); TECHNOLOGY; TESTING; THREE DIMENSIONAL; WAFER BONDING;

3-D MODELING; BALL CRATERING; BOND PADS; BONDING PROCESSES; BOROPHOSPHOSILICATE GLASS; BUMP BONDING; DIELECTRIC LAYERS; FLIP CHIP TECHNOLOGIES; FLIP CHIPPING; FREE AIR BALL; INTERNATIONAL CONFERENCES; MICRO-SYSTEMS; MULTI-PHYSICS SIMULATION; SIMULATION RESULTS; SOLDER BALLS; STUD BUMPING; WIRE-BONDING;

FLIP CHIP DEVICES;

EID: 49249112686     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESIME.2008.4525064     Document Type: Conference Paper

References (2)

1. Levine, L., Chaudhuri, A., and Stepniak, F., "Copper Stud Bumping for Flip-Chip Applications", Semiconductor International, June 2006.
2. Shin, M.S., and Kim, Y.H., "Microstructure Characterization of Sn-Ag Solder Joints between Stud Bumps and Metal Pads", Journal of Electronic Materials, Dec 2003.