Implementation of pipelined FastICA on FPGA for real-time blind source separation

IEEE Transactions on Neural Networks

Volumn 19, Issue 6, 2008, Pages 958-970

  Shyu, Kuo Kai ^a   Lee, Ming Huan ^a   Wu, Yu Te ^b,c   Lee, Po Lei ^a  

^a NATIONAL CENTRAL UNIVERSITY   (Taiwan)

^b NATIONAL YANG MING UNIVERSITY   (Taiwan)

^c TAIPEI VETERANS GENERAL HOSPITAL   (Taiwan)

Author keywords

Blind source separation (BSS); Fast independent component analysis (FastICA); Field programmable gate array (FPGA); Floating point (FP)

Indexed keywords

ARITHMETIC UNITS; FAST ICA; FAST INDEPENDENT COMPONENT ANALYSIS (FASTICA); FASTICA ALGORITHMS; FIELD-PROGRAMMABLE GATE ARRAY (FPGA); FLOATING POINT (FP); HAND CODING; HARDWARE DESCRIPTION LANGUAGES; MIXED SIGNALS; NON-GAUSSIAN; OFF-LINE METHODS; REAL-TIME SIGNAL PROCESSING; SAMPLING RATES;

APARTMENT HOUSES; COMPUTER HARDWARE DESCRIPTION LANGUAGES; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; INDEPENDENT COMPONENT ANALYSIS; LOGIC GATES; MAGNETOENCEPHALOGRAPHY; PIPELINE PROCESSING SYSTEMS; PIPELINES; SEPARATION; SEQUENTIAL SWITCHING; SIGNAL ANALYSIS; SIGNAL PROCESSING; SPEECH ANALYSIS;

BLIND SOURCE SEPARATION;

ALGORITHM; ARTICLE; ARTIFICIAL NEURAL NETWORK; AUTOMATED PATTERN RECOGNITION; COMPUTER; COMPUTER LANGUAGE; COMPUTER SIMULATION; HUMAN; PRINCIPAL COMPONENT ANALYSIS; SIGNAL PROCESSING; TIME;

ALGORITHMS; COMPUTER SIMULATION; COMPUTERS; HUMANS; NEURAL NETWORKS (COMPUTER); PATTERN RECOGNITION, AUTOMATED; PRINCIPAL COMPONENT ANALYSIS; PROGRAMMING LANGUAGES; SIGNAL PROCESSING, COMPUTER-ASSISTED; TIME FACTORS;

EID: 49149118836     PISSN: 10459227     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNN.2007.915115     Document Type: Article

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