A 180 Kbit embeddable MRAM memory module

IEEE Journal of Solid-State Circuits

Volumn 43, Issue 8, 2008, Pages 1826-1834

  Nahas, Joseph J ^d   Andre, Thomas W ^a   Garni, Brad ^b   Subramanian, Chitra ^a   Lin, Hal ^a   Alam, Syed M ^a   Papworth, Ken ^c   Martino, William L ^a  

^a Everspin Technologies   (United States)

^b FREESCALE SEMICONDUCTOR INC   (United States)

^c Everspin Technologies   (United States)

^d NONE

Author keywords

Magnetic memories; Magnetoresistance; Memory architecture; MRAM

Indexed keywords

ACCESS CONTROL; AMPLIFIERS (ELECTRONIC); AUTOMOBILE DRIVERS; ELECTRIC CURRENTS; MAGNETIC DEVICES; MAGNETIC STORAGE; OPTIMIZATION; SEMICONDUCTOR JUNCTIONS; STATIC RANDOM ACCESS STORAGE; TUNNEL JUNCTIONS; WAVEGUIDE JUNCTIONS;

BIT CELL; BIT LINES; CHARGE SHARING; CMOS PROCESSING; EMBEDDED TESTS; GROUND BOUNCE; INTERNAL MEMORY; MAGNETIC MEMORIES; MAGNETIC TUNNEL JUNCTION; MAGNETO-RESISTIVE RANDOM ACCESS MEMORY; MAGNETORESISTANCE; MEMORY ARCHITECTURE; MEMORY CELLS; MRAM; REFERENCE CURRENTS; REFERENCE VOLTAGES; SENSE AMPLIFIER; SENSE AMPLIFIERS; SWITCHED CAPACITORS; TWO STAGES; WORD LINES;

RANDOM ACCESS STORAGE;

EID: 48849095052     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.925408     Document Type: Conference Paper

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