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Volumn , Issue , 2007, Pages 67-71

Progresses and challenges of ant colony optimization-based evolvable hardware

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL MATHEMATICS; COMBINATORIAL OPTIMIZATION; DIGITAL ARITHMETIC; DIGITAL CIRCUITS; DIGITAL FILTERS; DIGITAL INTEGRATED CIRCUITS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; HEURISTIC ALGORITHMS; HEURISTIC METHODS; HEURISTIC PROGRAMMING; IIR FILTERS; NUMBER THEORY; RANDOM NUMBER GENERATION;

EID: 48749128167     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/WEAH.2007.361715     Document Type: Conference Paper
Times cited : (6)

References (31)
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  • 9
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    • FPGA implementation of population-based ant colony optimization
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  • 12
    • 79955148482 scopus 로고    scopus 로고
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    • A. Hämäläinen, M. Tommiska, J. Skyttä, 6.78 gigabits per second implementation of the IDEA cryptographic algorithm, in: M. Glesner, P. Zipf, M. Renovell (Eds.), Field-Programmable Logic and Applications. Reconfigurable Computing Is Going Mainstream, LNCS 2438, Springer-Verlag, pp. 760-769, 2002.
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    • Genetic algorithms in software and in hardware - a performance analysis of workstation and custom computing machine implementations
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    • Graham, P.1    Nelson, B.2
  • 16
    • 85014409954 scopus 로고    scopus 로고
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    • I.M. Bland, G.M. Megson, The systolic array genetic algorithm, an example of systolic arrays as a reconfigurable design methodology, in: IEEE Symposium on FPGAs for Custom Computing Machines, pp. 260-261, 1998.
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    • Bland, I.M.1    Megson, G.M.2
  • 18
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    • Time-scattered heuristic for the hardware implementation of population-based ACO
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.