Using hardware acceleration to reduce FPGA placement times

Canadian Conference on Electrical and Computer Engineering

Volumn , Issue , 2007, Pages 647-650

  Fobel, Christian ^a   Gréwal, Gary ^a   Morton, Andrew ^b  

^a UNIVERSITY OF GUELPH   (Canada)

^b UNIVERSITY OF WATERLOO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN FUNCTIONS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); ITERATIVE METHODS;

ELECTRICAL AND COMPUTER ENGINEERING (ECE); FIELD PROGRAMMABLE GATE ARRAY (FPGA); FIELD PROGRAMMABLE GATE ARRAY (FPGA) PLACEMENT; HARDWARE ACCELERATIONS; HARDWARE-ACCELERATED; ORDER-OF MAGNITUDES; SOFTWARE EXECUTION; TIME-CONSUMING PROCESSES;

COMPUTER HARDWARE;

EID: 48749087283     PISSN: 08407789     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CCECE.2007.166     Document Type: Conference Paper

References (5)

1. C. J. Alpert, T. Chan, D. Huang, I. Markov, and K. Yan, "Quadratic Placement Revisited," ACM/IEEE Design Automation Conference, pp. 752-757, 1997.
2. V. Betz and J. Rose, "VPR: A New Packing, Placement and Routing Tool for FPGA Research," Proceedings of the International Workshop on Field Programmable Logic and Applications, pp. 213-222, 1997.
3. V. Betz, J. Rose, and A. Marquardt, "Architecture and CAD for Deep-Submicron FPGAs", Kluwer Academic Publishers, ISBN 0-7923-8460-1, 1999.
4. A. DeHon, R. Huang, and J. Wawrzynek, "Hardware-Assisted Fast Routing," IEEE Symposium on Field-Programmable Custom Computing Machines, Napa, CA, 2002.
5. J. M. Kleinhans, G. Sigl, F. M., Johannes, and K. J. Antreich, "GORDIAN: VLSI Placement by Quadratic Programming and Slicing Optimization, " IEEE Transactions on Computer-Aided Design, 10(3):356-365, March, 1991.