A fast integrating ADC using precise time-to-digital conversion

IEEE Nuclear Science Symposium Conference Record

Volumn 1, Issue , 2007, Pages 302-304

  Fusayasu, Takahiro ^a  

^a NAGASAKI INSTITUTE OF APPLIED SCIENCE   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; DIGITAL ARITHMETIC; IMAGING TECHNIQUES; MEDICAL IMAGING; MULTICARRIER MODULATION; OPTICAL DESIGN; RANGE FINDING;

LAYOUT DESIGNS; NUCLEAR SCIENCES; SIMULATION STUDIES; TIME-TO-DIGITAL;

DIGITAL TO ANALOG CONVERSION;

EID: 48349136346     PISSN: 10957863     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NSSMIC.2007.4436335     Document Type: Conference Paper

References (6)

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2. E. Delagnes, D. Breton. F. Lugiez, and R. Rahmanifard. "A Low Power Multi-Channel Single Ramp ADC With Up to 3.2 GHz Virtual Clock", IEEE Trans. Nucl. Sci., Vol. 54, no. 5, pp. 1735-1742, Oct. 2007.
3. Y. Arai, T. Matsumura, and K. Endo, "A CMOS Four-Channel × 1K Time Memory LSI with 1-ns/b Resolution," IEEE J. Solid-State Circuits, vol. 27, no. 3, pp. 359-364, Mar. 1992.
4. E. R. Ruotsalainen, T. Rahkonen, and J. Kostamovaara, "A Low-Power CMOS Time-to-Digital Converter," IEEE J. Solid-State Circuits, vol. 30, no. 9, pp. 984-990, Sep. 1995.
5. J. P. Jansson, A. Maentyniemi, and J. Kostamovaara, "A CMOS Time-to-Digital Converter With Better Than 10 ps Single-Shot Precision," IEEE J. Solid-State Circuits, vol. 41, no. 6, pp. 1286-1296, Jun. 2006.
6. A. Maentyniemi, T. Rahkonen, and J. Kostamovaara, "A nonlinearity-corrected CMOS time digitizer IC with 20ps single-shot precision," Proc. IEEE Int. Symp. Circuits and Systems, May 2002, vol. 1, pp. 513-516.