Investigation into sub-threshold performance of double-gate accumulation-mode SOI PMOSFET

ASICON 2007 - 2007 7th International Conference on ASIC Proceeding

Volumn , Issue , 2007, Pages 1150-1153

  Zhang, Zhengfan ^a,b   Li, Zhaoji ^a   Tan, Kaizhou ^b   Zhang, Jiabin ^b  

^a UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA   (China)

^b NLAIC   (China)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC POWER SUPPLIES TO APPARATUS; ELECTRON BEAM LITHOGRAPHY;

ACCUMULATION MODES; ANALYTICAL MODELLING; DEPLETION APPROXIMATION; DOUBLE GATES; GATE OXIDE CAPACITANCE; INTERFACE TRAP DENSITY; INTERNATIONAL CONFERENCES; NUMERICAL SIMULATIONS; P-CHANNEL; PMOSFET; SOI-MOSFET; SUB-THRESHOLD SWING; THRESHOLD PERFORMANCE;

MOSFET DEVICES;

EID: 48349134962     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICASIC.2007.4415837     Document Type: Conference Paper

References (3)

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2. J. P. Colinge, D. FLANDRE, and F. VAN DE WIELE, Solid-state Electronics, 37, p.289 (1994).
3. Winokur P. S, Schwank J.R, and Mcwhortor P.J., IEEE Trans. Nucl. Sci, 31, p.1453 (1984).