Supporting high level language semantics within Hardware resident threads

Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL

Volumn , Issue , 2007, Pages 98-103

  Anderson, Erik ^a   Peck, Wesley ^a   Stevens, Jim ^a   Agron, Jason ^a   Baijot, Fabrice ^a   Warn, Seth ^a   Andrews, David ^a  

^a UNIVERSITY OF KANSAS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DISTRIBUTED MEMORIES; DYNAMIC MEMORY ALLOCATIONS; GENERALIZED FUNCTIONS; HARDWARE DESCRIPTIVE LANGUAGES; HARDWARE THREADS; LIBRARY FUNCTIONS; LOCAL VARIABLES; RECURSION; SOFTWARE THREADS; SYSTEM CALLS;

COMPUTER PROGRAMMING LANGUAGES; INFORMATION THEORY; LINGUISTICS; SEMANTICS;

HARDWARE;

EID: 48149111961     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2007.4380632     Document Type: Conference Paper

References (16)

1. J. Agron, W. Peck, and et al. Run-Time Services for Hybrid CPU/FPGA Systems on Chip. In Proc. of the 27th IEEE Int. Real-Time Systems Symp., pages 3-12, Rio De Janeiro, Dec. 2006.
2. E. Anderson, J. Agron, and et al. Enabling a Uniform Programming Model Across the Software/Hardware Boundary. In Proc. of 14th Annual IEEE Symp. on Field-Programmable Custom Computing Machines, pages 89-98, Napa, California, Apr. 2006.
3. D. Andrews, D. Niehaus, and et al. Programming Models for Hybrid FPGA/CPU Computational Components: A Missing Link. IEEE Micro, 24(4):42-53, July/August 2004.
4. D. Andrews, W. Peck, and et al. hThreads: A Hardware/Software Co-Designed Multithreaded RTOS Kernel. In Proc. of the 10th IEEE Int. Conference on Emerging Technologies and Factory Automation, Catania, Sept. 2005.
5. T. Callahan, J. R. Hauser, and J. Wawrzynek. The GARP Architecture and C Compiler. IEEE Computer, 33(4):62-69, 2000.
6. Celoxica. HandelC. http://www.celoxica.com.
7. S. C. Goldstein, H. Schmit, and et at. PipeRench: A Coprocessor for Streaming Multimedia Acceleration. In Proc. of the Int. Symp. on Computer Architecture, pages 28-39, 1999.
8. A. A. Jerraya and W. Wolf. Hardware/Software Interface Codesign for Embedded Systems. Computer, 38(2):63-69, 2005.
9. D. Lau, O. Pritchard, and P. Molson. Automated Generation of Hardware Accelerators with Direct Memory Access from ANSI/ISO Standard C Functions. In Proc. of 14th Annual IEEE Symp. on Field-Programmable Custom Computing Machines, pages 45-56, Napa, California, Apr. 2006.
10. L. Semeriaria, K. Sato, and G. D. Micheli. Resolution of dynamic memory allocation and pointers for the behavioral synthesis form C. In Proc. of Design Automation and Test in Europe, pages 312-319, 2000.
11. B. So, M. Hall, and P. Diniz. A Compiler Approach to Fast Hardware Design Space Exploration in FPGA-Based Systems. In Proc. of the Int. Conf. on Prog. Language Design and Implementation, pages 165-176, Berlin, June 2002.
12. J. Stevens and F. Baijot. Hybridthreads compiler. http://www.ittc.ku.edu/ hybrdithreads/downloads. Technical Report.
13. SystemC. Systemc. http://www.systemc.org.
14. M. Vuletic. Unifying Software and Hardware of Multi-threaded Reconfigurable Applications within Operating System Processes. PhD thesis, Ecole Polytechnique Federate de Lausanne, July 2006.
15. M. Vuletic, L. Pozzi, and P. Ienne. Seamless Hardware-Software Integration in Reconfigurable Computing Systems. IEEE Design and Test, 22(2): 102-113, 2005.
16. P. Wilson, M. Johnson, and D. Boles. Dynamic Storage Allocation, A Survey and Critical Review. In Int. Workshop Memory Management, Sept. 1995.