-
1
-
-
0029507865
-
Quantitative analysis of floating point arithmetic on FPGA based custom computing machine
-
IEEE
-
N. Shirazi, A. Walters, and P. Athanas, "Quantitative analysis of floating point arithmetic on FPGA based custom computing machine," in FPGAs for Custom Computing Machines. IEEE, 1995, pp. 155-162.
-
(1995)
FPGAs for Custom Computing Machines
, pp. 155-162
-
-
Shirazi, N.1
Walters, A.2
Athanas, P.3
-
2
-
-
0036385677
-
A flexible floating-point format for optimizing data-paths and operators in FPGA based DSPs
-
ACM
-
J. Dido, N. Geraudie, L. Loiseau, O. Payeur, Y. Savaria, and D. Poirier, "A flexible floating-point format for optimizing data-paths and operators in FPGA based DSPs," in Field-Programmable Gate Arrays. ACM, 2002, pp. 50-55.
-
(2002)
Field-Programmable Gate Arrays
, pp. 50-55
-
-
Dido, J.1
Geraudie, N.2
Loiseau, L.3
Payeur, O.4
Savaria, Y.5
Poirier, D.6
-
3
-
-
18644362604
-
A library of parameterized floating-point modules and their use
-
Field Programmable Logic and Applications, Springer
-
P. Belanović and M. Leeser, "A library of parameterized floating-point modules and their use," in Field Programmable Logic and Applications, ser. LNCS, vol. 2438. Springer, 2002, pp. 657-666.
-
(2002)
ser. LNCS
, vol.2438
, pp. 657-666
-
-
Belanović, P.1
Leeser, M.2
-
4
-
-
0038305296
-
Parameterisable floating-point operators on FPGAs
-
B. Lee and N. Burgess, "Parameterisable floating-point operators on FPGAs," in 36th Asilomar Conference on Signals, Systems, and Computers, 2002, pp. 1064-1068.
-
(2002)
36th Asilomar Conference on Signals, Systems, and Computers
, pp. 1064-1068
-
-
Lee, B.1
Burgess, N.2
-
5
-
-
35148852566
-
A tool for unbiased comparison between logarithmic and floating-point arithmetic
-
to appear
-
J. Detrey and F. de Dinechin, "A tool for unbiased comparison between logarithmic and floating-point arithmetic," Journal of VLSI Signal Processing, 2007, to appear.
-
(2007)
Journal of VLSI Signal Processing
-
-
Detrey, J.1
de Dinechin, F.2
-
6
-
-
84950148723
-
Using floating-point arithmetic on FPGAs to accelerate scientific N-body simulations
-
IEEE
-
G. Lienhart, A. Kugel, and R. Männer, "Using floating-point arithmetic on FPGAs to accelerate scientific N-body simulations," in FPGAs for Custom Computing Machines. IEEE, 2002.
-
(2002)
FPGAs for Custom Computing Machines
-
-
Lienhart, G.1
Kugel, A.2
Männer, R.3
-
7
-
-
20244390636
-
Floating-point sparse matrix-vector multiply for FPGAs
-
ACM
-
M. deLorimier and A. DeHon, "Floating-point sparse matrix-vector multiply for FPGAs," in Field-Programmable Gate Arrays. ACM, 2005, pp. 75-85.
-
(2005)
Field-Programmable Gate Arrays
, pp. 75-85
-
-
deLorimier, M.1
DeHon, A.2
-
8
-
-
20344376214
-
64-bit floating-point FPGA matrix multiplication
-
ACM
-
Y. Dou, S. Vassiliadis, G. K. Kuzmanov, and G. N. Gaydadjiev, "64-bit floating-point FPGA matrix multiplication," in Field-Programmable Gate Arrays. ACM, 2005, pp. 86-95.
-
(2005)
Field-Programmable Gate Arrays
, pp. 86-95
-
-
Dou, Y.1
Vassiliadis, S.2
Kuzmanov, G.K.3
Gaydadjiev, G.N.4
-
9
-
-
33846568026
-
A parameterized floating-point exponential function for FPGAs
-
IEEE, Dec
-
J. Detrey and F. de Dinechin, "A parameterized floating-point exponential function for FPGAs," in Field-Programmable Technology. IEEE, Dec. 2005.
-
(2005)
Field-Programmable Technology
-
-
Detrey, J.1
de Dinechin, F.2
-
11
-
-
0016961904
-
Should the elementary functions be incorporated into computer instruction sets?
-
June
-
G. Paul and M. W. Wilson, "Should the elementary functions be incorporated into computer instruction sets?" ACM Transactions on Mathematical Software, vol. 2, no. 2, pp. 132-142, June 1976.
-
(1976)
ACM Transactions on Mathematical Software
, vol.2
, Issue.2
, pp. 132-142
-
-
Paul, G.1
Wilson, M.W.2
-
12
-
-
0026171455
-
Table lookup algorithms for elementary functions and their error analysis
-
IEEE, June
-
P. T. P. Tang, "Table lookup algorithms for elementary functions and their error analysis," in 10th Symposium on Computer Arithmetic. IEEE, June 1991.
-
(1991)
10th Symposium on Computer Arithmetic
-
-
Tang, P.T.P.1
-
14
-
-
0037511912
-
IA-64 and Elementary Functions: Speed and Precision
-
Prentice Hall
-
P. Markstein, IA-64 and Elementary Functions: Speed and Precision, ser. Hewlett-Packard Professional Books. Prentice Hall, 2000.
-
(2000)
ser. Hewlett-Packard Professional Books
-
-
Markstein, P.1
-
15
-
-
35148894691
-
A study on the design of floating-point functions in FPGAs
-
Field Programmable Logic and Applications, Springer, Sept
-
F. Ortiz, J. Humphrey, J. Durbano, and D. Prather, "A study on the design of floating-point functions in FPGAs," in Field Programmable Logic and Applications, ser. LNCS, vol. 2778. Springer, Sept. 2003, pp. 1131-1135.
-
(2003)
ser. LNCS
, vol.2778
, pp. 1131-1135
-
-
Ortiz, F.1
Humphrey, J.2
Durbano, J.3
Prather, D.4
-
16
-
-
18644383778
-
-
C. Doss and R. L. Riley, Jr., FPGA-based implementation of a robust IEEE-754 exponential unit, in Field-Programmable Custom Computing Machines. IEEE, 2004, pp. 229-238.
-
C. Doss and R. L. Riley, Jr., "FPGA-based implementation of a robust IEEE-754 exponential unit," in Field-Programmable Custom Computing Machines. IEEE, 2004, pp. 229-238.
-
-
-
-
18
-
-
0006432892
-
-
SunPro, Mountain View, CA, USA, Technical Report, July
-
K. C. Ng, "Argument reduction for huge arguments: good to the last bit," SunPro, Mountain View, CA, USA, Technical Report, July 1992.
-
(1992)
Argument reduction for huge arguments: Good to the last bit
-
-
Ng, K.C.1
-
19
-
-
0000821687
-
Modular range reduction: A new algorithm for fast and accurate computation of the elementary functions
-
Mar
-
M. Daumas, C. Mazenc, X. Merrheim, and J. M. Muller, "Modular range reduction: A new algorithm for fast and accurate computation of the elementary functions," Journal of Universal Computer Science, vol. 1, no. 3, pp. 162-175, Mar. 1995.
-
(1995)
Journal of Universal Computer Science
, vol.1
, Issue.3
, pp. 162-175
-
-
Daumas, M.1
Mazenc, C.2
Merrheim, X.3
Muller, J.M.4
-
20
-
-
32044440559
-
Double-residue modular range reduction for floating-point hardware implementations
-
Mar
-
J. Villalba, T. Lang, and M. A. Gonzalez, "Double-residue modular range reduction for floating-point hardware implementations," IEEE Transactions on Computers, vol. 55, no. 3, pp. 254-267, Mar. 2006.
-
(2006)
IEEE Transactions on Computers
, vol.55
, Issue.3
, pp. 254-267
-
-
Villalba, J.1
Lang, T.2
Gonzalez, M.A.3
|