SCOPUS 정보 검색 플랫폼

2007 International Symposium on System-on-Chip Proceedings, SOC

Volumn , Issue , 2007, Pages

Mapping streaming applications on a reconfigurable MPSoC platform at run-time

(3) Hölzenspies, Philip K F a Smit, Gerard J M a Kuper, Jan a

a UNIVERSITY OF TWENTE (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BANDWIDTH; CONFORMAL MAPPING; ELECTRIC NETWORK TOPOLOGY; INTEGRATED CIRCUITS; TELECOMMUNICATION NETWORKS;

APPLICATIONS.; BOUNDED LATENCY; GUARANTEED BANDWIDTH; HARDWARE ARCHITECTURE; INTERNATIONAL SYMPOSIUM; NETWORK INTERFACES; NETWORK ON CHIPS; PERFORMANCE MODELLING; PROCESSING ELEMENTS; RE-CONFIGURABLE; REAL-TIME REQUIREMENTS; RECONFIGURABLE PROCESSING; RUN-TIME; STREAMING APPLICATIONS; SYSTEM ON CHIPS;

PROGRAMMABLE LOGIC CONTROLLERS;

EID: 48049117550 PISSN: None EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/ISSOC.2007.4427443 Document Type: Conference Paper

Times cited : (12)

References (10)

1
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- Stream Processors: Programmability with Efficiency
- March
- William Dally et al. "Stream Processors: Programmability with Efficiency" ACM Queue, March 2004, pp. 52-62
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- Dally, W.¹

2
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- P. M. Heysters, Coarse-grained reconfigurable processors, CTIT Ph.D.-thesis series No. 04-66, 2004.
- P. M. Heysters, "Coarse-grained reconfigurable processors", CTIT Ph.D.-thesis series No. 04-66, 2004.

3
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- RAMP: Research Accelerator for Multiple Processors
- Palo Alto, CA, August
- D. Patterson, Arvind, K. Asanovic, D. Chiou, J. Hoe, C Kozyrakis, S. Lu, M. Oskin, J. Rabaey, J. Wawrzynek, "RAMP: Research Accelerator for Multiple Processors," Technical Record of the 18th Hot Chips Symposium, Palo Alto, CA, August 2006
- (2006) Technical Record of the 18th Hot Chips Symposium
- Patterson, D.¹ Arvind² Asanovic, K.³ Chiou, D.⁴ Hoe, J.⁵ Kozyrakis, C.⁶ Lu, S.⁷ Oskin, M.⁸ Rabaey, J.⁹ Wawrzynek, J.¹⁰

4
- 48049116442
- http://www.smart-chips.net

5
- 33847189561
- Run-time Mapping of Applications to a Heterogeneous SoC
- Tampere, Finland, pp, November
- L.T. Smit, J.L. Hurink, G.J.M. Smit: "Run-time Mapping of Applications to a Heterogeneous SoC", In: Proceedings 2005 International Symposium on System-on-Chip, Tampere, Finland, pp. 78-81, November 2005
- (2005) Proceedings 2005 International Symposium on System-on-Chip , pp. 78-81
- Smit, L.T.¹ Hurink, J.L.² Smit, G.J.M.³

6
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- A virtual channel router for on-chip networks
- IEEE Computer Society Press, September
- N. Kavaldjiev, G. J. M. Smit, and P. G. Jansen. "A virtual channel router for on-chip networks" In Proceedings of IEEE International SOC Conference, pages 289-293. IEEE Computer Society Press, September 2004.
- (2004) Proceedings of IEEE International SOC Conference , pp. 289-293
- Kavaldjiev, N.¹ Smit, G.J.M.² Jansen, P.G.³

7
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- Synchronous dataflow
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- E. A. Lee et al. "Synchronous dataflow.", Proceedings of the IEEE, 75(9):1235{1245, September 1987.
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8
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- Hierarchical static scheduling of dataflow graphs onto multiple processors
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9
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- Hydra: An Energy-efficient and Reconfigurable Network Interface
- M.D. van de Burgwal, G.J.M. Smit, G.K. Rauwerda, P.M. Heysters, "Hydra: an Energy-efficient and Reconfigurable Network Interface" In: Proceedings of ERSA2006, 26-29 June 2006
- (2006) Proceedings of ERSA2006, 26-29 June
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10
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- Vangal, Sriram et al: An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS, proceedings ISCC 2007, pp 98-99
- Vangal, Sriram et al: "An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS", proceedings ISCC 2007, pp 98-99

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.