A digital circuit for jitter reduction of GPS-disciplined 1-pps synchronization signals

AMUEM 2007 - Proceedings of the 2007 IEEE International Workshop on Advanced Methods for Uncertainty Estimation in Measurement

Volumn , Issue , 2007, Pages 84-88

  Gasparini, L ^a   Zadedyurina, O ^a   Fontana, G ^a   Macii, D ^a   Boni, A ^a   Ofek, Y ^a  

^a UNIVERSITY OF TRENTO   (Italy)

Author keywords

1 pps; GPS; Jitter measurements; Phase lock loops; Signal processing; Synchronization

Indexed keywords

ATOMIC PHYSICS; DIGITAL ARITHMETIC; DIGITAL INTEGRATED CIRCUITS; ESTIMATION; FREQUENCY STANDARDS; GLOBAL POSITIONING SYSTEM; SATELLITE NAVIGATION AIDS; SIGNAL RECEIVERS; SYNCHRONIZATION; SYSTEM STABILITY; TIME MEASUREMENT; TIMING CIRCUITS; UNCERTAINTY ANALYSIS;

1-PPS; GLOBAL POSITIONING SYSTEM (GPS); GPS; GPS RECEIVERS; JITTER MEASUREMENTS; PHASE LOCK LOOPS; SETTLING TIME; SIGNAL PROCESSING; SYNCHRONIZATION CIRCUITS; SYNCHRONIZATION SIGNALS; UNCERTAINTY ESTIMATION;

JITTER;

EID: 48049084136     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/AMUEM.2007.4362576     Document Type: Conference Paper

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