Synthesis of DSP architectures using libraries of coarse-grain configurations

IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

Volumn , Issue , 2007, Pages 475-480

  Salmela, Perttu ^a   Shen, Chung Ching ^b   Bhattacharyya, Shuvra S ^b   Takala, Jarmo ^a  

^a TAMPERE UNIVERSITY OF TECHNOLOGY   (Finland)

^b UNIVERSITY OF MARYLAND   (United States)

Author keywords

Exploration; ILP; Multiobjective; System design

Indexed keywords

ELECTRIC POWER UTILIZATION; EVOLUTIONARY ALGORITHMS; MULTIOBJECTIVE OPTIMIZATION; OPTIMIZATION; SIGNAL PROCESSING; SYSTEMS ANALYSIS; TECHNICAL PRESENTATIONS;

CLOCK FREQUENCIES; COMPUTING RESOURCES; COST METRICS; DESIGN SPACES; DSP ARCHITECTURES; EXPLORATION; GENERAL FRAMEWORKS; HARDWARE DESIGNS; ILP; INSTRUCTION LEVEL PARALLELISMS; MULTI SETS; MULTI-OBJECTIVE EVOLUTIONARY ALGORITHMS; MULTI-OBJECTIVE OPTIMIZATIONS; MULTIOBJECTIVE; POWER CONSUMPTIONS; PROCESSING LATENCIES; RAKE RECEIVERS; SYSTEM DESIGN; TIME SIGNALS;

DESIGN;

EID: 47949114350     PISSN: 15206130     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SIPS.2007.4387594     Document Type: Conference Paper

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