Intel's post silicon functional validation approach

Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT

Volumn , Issue , 2007, Pages 53-55

  Tommy, Bojan ^a   Igor, Frumkin ^a   Robert, Mauri ^b  

^a INTEL CORPORATION   (Israel)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUDGET CONTROL; LEAD; PROGRAM DEBUGGING; SILICON; TESTING;

BUDGET CONSTRAINTS; COMPLEX ARCHITECTURES; FUNCTIONAL VALIDATION; HARD WORK; HIGH AUTOMATION; HIGH LEVEL DESIGNS; HIGH-QUALITY PRODUCTS; INTEL CORPORATION (CO); INTERNATIONAL (CO); SILICON DEBUG; VALIDATION PROCESSES;

NONMETALS;

EID: 47949099868     PISSN: 15526674     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HLDVT.2007.4392786     Document Type: Conference Paper

References (4)

1. Intel Corporation, "Intel® 64 and IA-32 Architectures Software Developer's Manual" (PRM), Vol 1, 2a, 2b & 3, Nov. 2006.
2. Intel Corporation, Internal Intel Specific Documentation
3. IEEE 1149.1, Test Access Port and Boundary-scan architecture (2001)
4. T. Bojan, I. Frumkin, R. Mauri Intel® First Ever Converged Core Functional Validation Experience: Challenges, Methodologies, Results and Learning. Submitted to Microprocessor Test & Verification Conference, Austin, Dec. 2007 (in preparation).