An architecture based on reconfigurability and asynchronism for real-time image processing

Journal of Real-Time Image Processing

Volumn 3, Issue 3, 2008, Pages 119-130

  Denoulet, Julien ^a   Mérigot, Alain ^b  

^a SORBONNE UNIVERSITÉ   (France)

^b UNIVERSITÉ PARIS SACLAY   (France)

Author keywords

Associative nets model; Asynchronism; Motion detection; Parallel architecture; Segmentation; SIMD; Vision SoC

Indexed keywords

ASSOCIATIVE PROCESSING; IMAGE SEGMENTATION; MESH GENERATION; MOTION ANALYSIS; PROGRAMMABLE LOGIC CONTROLLERS; RECONFIGURABLE ARCHITECTURES; SYSTEM-ON-CHIP;

ASSOCIATIVE NETS MODEL; ASYNCHRONISM; MOTION DETECTION; SIMD; VISION SOC;

PARALLEL ARCHITECTURES;

EID: 47849119999     PISSN: 18618200     EISSN: None     Source Type: Journal    
DOI: 10.1007/s11554-007-0063-8     Document Type: Article

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