Performance evaluation of instruction set extensions for long integer modular arithmetic on a SPARC V8 processor

Proceedings - 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, DSD 2007

Volumn , Issue , 2007, Pages 680-689

  Großschädl, Johann ^a   Tillich, Stefan ^a   Szekely, Alexander ^a  

^a GRAZ UNIVERSITY OF TECHNOLOGY   (Austria)

Author keywords

[No Author keywords available]

Indexed keywords

CRYPTOGRAPHY; DIGITAL ARITHMETIC; DIGITAL SIGNAL PROCESSING; MICROPROCESSOR CHIPS; PUBLIC KEY CRYPTOGRAPHY; SMART CARDS; SYSTEMS ANALYSIS; TELECOMMUNICATION EQUIPMENT;

ARITHMETIC OPERATIONS; CLOCK CYCLES; CODE SIZES; CRYPTOSYSTEMS; CUSTOM INSTRUCTIONS; EMBEDDED DEVICES; EXECUTION TIMES; EXPONENTIATION; INNER LOOPS; INSTRUCTION SET EXTENSIONS; INTEGER ARITHMETICS; LOOP UNROLLING; MEMORY REQUIREMENTS; MODULAR ARITHMETICS; MODULAR EXPONENTIATION; MODULAR MULTIPLICATIONS; PERFORMANCE EVALUATIONS; PERFORMANCE GAINS; REASONABLE VALUES; SENSOR NODES; SIGNIFICANT IMPACTS; SPARC V8 PROCESSORS; WINDOW METHODS;

ARCHITECTURAL DESIGN;

EID: 47749100816     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2007.4341542     Document Type: Conference Paper

References (34)

1. ARM Limited. SecurCore™ Solutions. Product brief, available for download at http://www.arm.com/miscPDFs/1665.pdf, 2002.
2. ARM Limited. ARM Architecture Reference Manual. ARM Doc No. DDI-0100, Issue H, 2003.
3. P. G. Comba. Exponentiation cryptosystems on the IBM PC. IBM Systems Journal, 29(4):526-538, Dec. 1990.
4. J.-F. Dhem. Design of an efficient public-key cryptographic library for RISC-based smart cards. Ph.D. Thesis, Université Catholique de Louvain, Belgium, 1998.
5. W. Diffie and M. E. Hellman. New directions in cryptography. IEEE Transactions on Information Theory, 22(6):644-654, Nov. 1976.
6. S. R. Dussé and B. S. Kaliski. A cryptographic library for the Motorola DSP56000. In Advances in Cryptology - EUROCRYPT '90, LNCS 473, pp. 230-244. Springer Verlag, 1991.
7. H. Eberle, S. Chang Shantz, V. Gupta, N. Gura, L. D. Rarick, and L. A. Spracklen. Accelerating next-generation public-key cryptosystems on general-purpose CPUs. IEEE Micro, 25(2):52-59, Mar. 2005.
8. J. Gaisler. The LEON-2 Processor User's Manual (Version 1.0.30). Available for download at http://www.gaisler.com, 2005.
9. J. Großschädl and G.-A. Kamendje. Architectural enhancements for Montgomery multiplication on embedded RISC processors. In Applied Cryptography and Network Security - ACNS 2003, LNCS 2846, pp. 418-434. Springer Verlag, 2003.
10. J. Großschädl, A. Szekely, and S. Tillich. Algorithm exploration for long integer modular arithmetic on a SPARC V8 processor with cryptography extensions. In Proceedings of the 2nd Int. Conference on Embedded Software and Systems (ICESS 2005), pp. 187-194. IEEE Computer Society Press, 2005.
11. J. Großschädl, S. Tillich, A. Szekely, and M. Wurm. Cryptography instruction set extensions to the SPARC V8 architecture. Preprint, submitted for publication, 2007.
12. M. K. Gschwind. Instruction set selection for ASIP design. In Proceedings of the 7th Int. Symposium on Hardware/Software Codesign (CODES '99), pp. 7-11. ACM Press, 1999.
13. Intel Corporation. Intel® IA-64 Architecture Software Reference Manual, Volume 3: Instruction Set Reference (Revision 1.1). Document Number: 245319-002, July 2000.
14. R. Holly. A reusable Duff device. Dr. Dobb's Journal 30(8):73-74, Aug. 2005.
15. Intel Corporation. Intel® Itanium™ Processor: High performance on security algorithms (RSA decryption kernel). Test report, available for dowload at http://www.intel.com/cd/ids/developer/asmo-na/eng/dc/itanium/ optimization/80661.htm, 2000.
16. Ç. K. Koç. High-speed RSA implementation. Technical Report TR 201 (Nov. 1994), RSA Data Security, Inc. Available for download at ftp://ftp.rsasecurity.com/pub/pdfs/tr201.pdf.
17. Ç. K. Koç, T. Acar, and B. S. Kaliski. Analyzing and comparing Montgomery multiplication algorithms. IEEE Micro, 16(3):26-33, June 1996.
18. K. Kücu̧ükçakar. An ASIP design methodology for embedded systems. In Proceedings of the 7th Int. Symposium on Hardware/Software Codesign (CODES '99), pp. 17-21. ACM Press, 1999.
19. A. J. Menezes, P. C. van Oorschot, and S. A. Vanstone. Handbook of Applied Cryptography. CRC Press, 1996.
20. MIPS Technologies, Inc. SmartMIPS™ Architecture Smart Card Extensions. Product brief, available for download at http://www.mips.com, 2001.
21. MIPS Technologies, Inc. Making smart cards secure. The Pipeline (Technology Newsletter), p. 4, Fall 2001. Available for download at http://www.mips.com.
22. MIPS Technologies, Inc. MIPS32™ Architecture for Programmers Volume IV-d: The SmartMIPS™ Application-Specific Extension to the MIPS32™ Architecture. Available for download at http://www.mips.com, 2003.
23. P. L. Montgomery. Modular multiplication without trial division. Mathematics of Computation, 44(170):519-521, Apr. 1985.
24. NEC Electronics Europe GmbH. V-WAY32 32-bit Security Cryptocontroller. Product letter, available for download at http://www.eu.necel.com/_pdf/ U16674EE1V0PL00.PDF, Apr. 2003.
25. D. A. Patterson and J. L. Hennessy. Computer Organization and Design: The Hardware/Software Interface. Morgan Kaufmann, 2004.
26. R. P. Paul. SPARC® Architecture, Assembly Language Programming, and C. Prentice Hall, 2nd edition, 2000.
27. B. J. Phillips and N. Burgess. Implementing 1,024-bit RSA exponentiation on a 32-bit processor core. In Proceedings of the 12th IEEE Int. Conference on Application-specific Systems, Architectures and Processors (ASAP 2000), pp. 127-137. IEEE Computer Society Press, 2000.
28. R. L. Rivest, A. Shamir, and L. M. Adleman. A method for obtaining digital signatures and public key cryptosystems. Communications of the ACM, 21(2):120-126, Feb. 1978.
29. M. P. Scott. Comparison of methods for modular exponentiation on 32-bit Intel 80x86 processors. Draft, available for download at ftp://ftp.computing. dcu.ie/pub/crypto/timings.ps, 1996.
30. H. Sharangpani and K. Arora. Itanium processor microarchitecture. IEEE Micro, 20(5):24-43, Sept./Oct. 2000.
31. N. P. Smart. Physical side-channel attacks on cryptographic systems. Software Focus, 1(2):6-13, Dec. 2000. Available online at http://www.wiley.co.uk/softwarefocus/web.pdf.
32. SPARC International, Inc. The SPARC Architecture Manual Version 8 (Revision SAV080SI9308). Available for download at http://www.sparc.org/ standards/V8.pdf, 1993.
33. STMicroelectronics, Inc. ST22XJ64 smartcard 32-bit RISC MCU with 64 kbytes EEPROM and Javacard™ hardware execution. Data Briefing, Sept. 2001.
34. Sun Microsystems, Inc. Sun Microsystems completes design tape-out for next-generation, breakthrough UltraSPARC T2 CoolThreads processor. Press Release, available online at http://www.sun.com/smi/Press/sunflash/2006-04/ sunflash.20060412.2.xml, 2006.