Scaling analytical models for soft error rate estimation under a multiple-fault environment

Proceedings - 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, DSD 2007

Volumn , Issue , 2007, Pages 641-648

  Hescott, Christian J ^a   Ness, Drew C ^b   Lilja, David J ^a  

^a University of Minnesota   (United States)

^b UNIVERSITY OF MINNESOTA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURAL DESIGN; ERROR CORRECTION; FAILURE ANALYSIS; FAULT TOLERANCE; FAULT TOLERANT COMPUTER SYSTEMS; FAULT TREE ANALYSIS; MICROPROCESSOR CHIPS; MODAL ANALYSIS; NETWORKS (CIRCUITS); QUALITY ASSURANCE; RELIABILITY; SYSTEMS ANALYSIS;

ANALYTICAL MODELS; AND GATES; BRANCHING EFFECTS; CIRCUIT SENSITIVITIES; ESTIMATION ALGORITHMS; INTER-DEPENDENCES; MULTIPLE FAULTS; PERMANENT FAULTS; SOFT ERROR RATE ESTIMATIONS; SOFT ERROR RATES; SOFT ERRORS; TRANSIENT FAULTS; TRIPLE MODULAR REDUNDANCIES;

CIRCUIT SIMULATION;

EID: 47749091269     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2007.4341535     Document Type: Conference Paper

References (6)

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