Energy-aware interconnect optimization for a coarse grained reconfigurable processor

Proceedings of the IEEE International Frequency Control Symposium and Exposition

Volumn , Issue , 2008, Pages 201-207

  Lambrechts, Andy ^a,b   Raghavan, Praveen ^a,b   Jayapala, Murali ^a,c   Catthoor, Francky ^a,b   Verkest, Diederik ^a,c  

^a IEEE

^b UNIVERSITY OF LEUVEN   (Belgium)

^c IMEC   (Belgium)

Author keywords

Energy aware design; Interconnect aware design; Low power; Processor architecture

Indexed keywords

ENERGY POLICY; TOPOLOGY; WIRELESS SENSOR NETWORKS;

APPLICATION DOMAINS; BATTERY LIFE; COARSE GRAINED RECONFIGURABLE ARCHITECTURES (CGRAS); COARSE GRAINING; COMPUTATIONAL RESOURCES; CONNECTIONS (STRUCTURAL); EMBEDDED DEVICES; ENERGY AWARE; ENERGY CONSTRAINTS; ENERGY COSTS; INTER CONNECTS; INTERCONNECT OPTIMIZATION; INTERCONNECTION TOPOLOGIES; INTERNATIONAL CONFERENCES; PERFORMANCE TRADE-OFF; RECONFIGURABLE PROCESSORS; STATE OF THE ARTS; TOTAL ENERGY CONSUMPTION; VLSI DESIGNS; WIDE-RANGE; WIRELESS APPLICATIONS;

OPTIMIZATION;

EID: 47649119254     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSI.2008.25     Document Type: Conference Paper

References (16)

1. N. Bansal, S. Gupta, N. Dutt, A. Nicolau, and R. Gupta. Network topology exploration of mesh-based coarse-grain reconfigurable architectures. In Proc. of Design Automation and Test in Europe (DATE), 2004.
2. L. Benini, D. Bruni, M. Chinosi, C. Silvano, and V. Zacearia. A power modeling and estimation framework for vliw-based embedded system. ST Journal of System Research, 3(1):110-118, April 2002. (Also presented in PATMOS 2001).
3. D. Burger, S. Keckler, and K. McKinley. Scaling to the end of silicon with edge architectures. In IEEE Computer, volume 37(7), pages 44-55, 2004.
4. J. Y. Chen, W. B. Jone, J. S. Wang, H.-I. Lu, and T. F. Chen. Segmented bus design for low-power systems. IEEE Transactions on VLSI Systems, 7(1), March 1999.
5. H. DeMan. Ambient intelligence: Giga-scale dreams and nano-scale realities. In Proc of ISSCC. Keynote Speech, February 2005.
6. F.Bouwens, M.Berekovic, A.Kanstein, and G.Gaydadjiev. Architectural exploration of the adres coarse-grained reconfigurable array. In Proceedings of ARC, 2007.
7. Z. Kwok and S. Wilton. Register file architecture optimization in a coarse-grained reconfigurable architecture. In Proc of FCCM, April 2005.
8. A. Lambrechts, P. Raghavan, M. Jayapala, D. Verkest, and F. Catthoor. Energy-aware interconnect-exploration of coarse grained reconfigurable processors. In IEEE Workshop on Application Specific Processors, September 2005.
9. G. Lu, H. Singh, M. Lee, N. Bagherzadeh, F. Kurdahi, and E. Filho. The MorphoSys parallel reconfigurable system. In Proc of Euro-Par, 1999.
10. B. Mei, S. Vernalde, D. Verkest, H. D. Man, and R. Lauwereins. DRESC: A retargetable compiler for coarse-grained reconfigurable architectures. In Proc. of International Conference on Field Programmable Technology, pages 166-173, 2002.
11. B. Mei, S. Vernalde, D. Verkest, H. D. Man, and R. Lauwereins. ADRES: An architecture with tightly coupled vliw processor and coarse-grained reconfigurable matrix. In Proc of FPL, 2003.
12. Montium TP Processor, http://www.recoresystems.com. Montium Tile Processor Reference Manual, 2005.
13. D. Novo, B. Bougard, P. Raghavan, H. Souk, and L. V. der Perre. Energy-performance exploration of a cga-based sdr processor. In Proc of SDR Forum, 2006.
14. Philips Research, http://www.siliconhive.com. Philips SiliconHive Avispa Accelerator.
15. P.Raghavan, A.Lambrechts, M.Jayapala, F.Catthoor, and D.Verkest. EMPIRE: Empirical power/area/timing models for register files. In International Journal on Embedded Systems (special issue on Media and Stream Processing), 2006. To appear.
16. Sandbridge Technologies, http://www.sandbridgetech.com. The Sandblaster Architecture.