Verifying correctness of transactional memories

Proceedings - Formal Methods in Computer Aided Design, FMCAD 2007

Volumn , Issue , 2007, Pages 37-44

  Cohen, Ariel ^a   O'Leary, John W ^b   Pnueli, Amir ^a   Turtle, Mark R ^b   Zuck, Lenore D ^c  

^a CS/CIMS/NYU

^b INTEL CORPORATION   (United States)

^c CS/UIC ^*

Author keywords

HTM; Model checking; STM; TLA+; TLC; Transactional memory; Verification

Indexed keywords

MODEL CHECKERS; TRANSACTIONAL MEMORY (TM);

COMPUTER AIDED DESIGN; DATA STORAGE EQUIPMENT; FORMAL METHODS; INTERCHANGES; INTERSECTIONS; STORAGE ALLOCATION (COMPUTER);

MODEL CHECKING;

EID: 47349122939     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FAMCAD.2007.40     Document Type: Conference Paper

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