Power and failure analysis of CAM cells due to process variations

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn , Issue , 2006, Pages 608-611

  Bennaser, Mahmoud ^a   Moritz, Csaba Andras ^a  

^a University of Massachusetts   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS TECHNOLOGIES; EFFECTIVE CHANNEL LENGTH; ELECTRICAL PARAMETERS; INDIVIDUAL (PSS 544-7); INTERNATIONAL CONFERENCES; PARAMETER VALUES; PROCESS VARIATIONS; STRENGTH (IGC: D5/D6);

ASSOCIATIVE STORAGE; CAMS; QUALITY ASSURANCE; RELIABILITY; SAFETY FACTOR;

FAILURE ANALYSIS;

EID: 47349121594     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2006.379862     Document Type: Conference Paper

References (5)

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3. Q. Chen, H. Mahmoodi, S. Bhunia, and K. Roy. Modeling and testing of sram for new failure mechanisms due to process variations in nanoscale cmos. In VLSI Test Symposium (VTS), May 2005.
4. S. Furber. Arm system-on-chip architecture. Addison-Wesley, 2000.
5. M. Zhang and K. Asanovic. Highly-associative caches for low-power processors. In Kool Chips Workshop, 33rd International Symposium on Microarchitecture, December 2000.