Writing portable applications that dynamically bind at run time to reconfigurable hardware

Proceedings 2007 IEEE Symposium on Field-Programme Custom Computing Machines, FCCM 2007

Volumn , Issue , 2007, Pages 229-238

  Moore, Nicholas ^a   Conti, Albert ^a   Leeser, Miriam ^a   King, Laurie Smith ^b  

^a Northeastern University   (United States)

^b Department of Biology   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CODES (SYMBOLS); COMPUTER HARDWARE; RECONFIGURABLE ARCHITECTURES;

EMERGING ARCHITECTURES; EXTENSIBLE FRAMEWORK; PERFORMANCE BENEFITS; PORTABLE APPLICATIONS; PROGRAMMABLE PROCESSORS; RECONFIGURABLE COMPUTING; RESOURCE MANAGEMENT; SPECIFIC HARDWARE;

RECONFIGURABLE HARDWARE;

EID: 47349086938     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FCCM.2007.39     Document Type: Conference Paper

References (17)

1. E. Anderson, J. Argon, et al. Enabling a uniform programming model across the soft-ware/hardware boundary. In IEEE Symposium on FPGAs for Custom Computing Machines (FCCM), April 2006.
2. A. A. Conti. A hardware/software system for adaptive beamforming. Master's thesis, Dept. of ECE, Northeastern University, December 2006.
3. Cray XD1. http://cray.com/products/xd1/ index.html. Last accessed 29 November 2006.
4. R. Deville, I. Troxel, and A. George. Performance monitoring for run-time management of reconfigurable devices. In Engineering of Reconfigurable Systems and Algorithms (ERSA), June 2005.
5. M. Franklin, J. Maschmeyer, et al. Auto-pipe: a pipeline design and evalutation system. In International Parallel and Distributed Processing Symposium (IPDPS), April 2006.
6. P. Graham and B. E. Nelson. FPGA-based sonar processing. In ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pages 201-208, 1998.
7. B. Holland, J. Greco, et al. Compile- and runtime services for distributed heterogeneous reconfigurable computing. In Engineering of Reconfigurable Systems and Algorithms (ERSA), June 2006.
8. HPEC-SI. VSIPL++: Vector Signal Image Processing Library. http://www.hpec-si.org, Last accessed 28 August 2006.
9. B. L. Hutchings and B. E. Nelson. GigaOp DSP on FPGA. The Journal of VLSI Signal Processing, 36(1):41-55, November 2004.
10. S. Leeper, R. Haney, H. Nguyen, and M. Vai. FPGA beamforming in a wideband airborne radar system. In High Performance Embedded Computing, September 2003.
11. Mercury PowerStream. http://mc.com/products/view/index.cfm?id= 19&type=systems. Last accessed 30 November 2006.
12. N. Moore, A. Conti, L. King, and M. Leeser. An extensible framework for application portability between reconfigurable supercomputing architectures. IEEE Computer Magazine, pages 39-49, March 2007.
13. W. Peck, E. Anderson, et al. Hthreads: a computational model for reconfigurable devices. In Field Programmable Logic and Applications, August 2006.
14. SGI RASC. http://www.sgi.com/products/rasc/. Last accessed 29 November 2006.
15. SRC-7. http://srccomputers.com/SRC7.htm. Last accessed 28 August 2006.
16. B. D. Van Veen and K. M. Buckley. Beam-forming: a versatile approach to spatial filtering. IEEE ASSP Magazine, 5(2):4-24, April 1988.
17. M. Vuletic, L. Pozzi, and P. Ienne. Seamless hardware-software integration in reconfigurable computing systems. IEEE Design and Test of Computers, 22(2):102-113, 2005.