Performance improvement methodology for ClearSpeed's CSX600

Proceedings of the International Conference on Parallel Processing

Volumn , Issue , 2007, Pages

  Nishikawa, Yuri ^a   Koibuchi, Michihiro ^b   Yoshimi, Masato ^a   Miura, Kenichi ^b   Amano, Hideharu ^a  

^a KEIO UNIVERSITY   (Japan)

^b NATIONAL INSTITUTE OF INFORMATICS   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK TOPOLOGY; MULTITASKING; TELECOMMUNICATION SYSTEMS;

ARRAY STRUCTURES; CO PROCESSORS; DATA FLOWS; INTERNATIONAL CONFERENCES; LOCAL MEMORIES; MULTI THREADING; NETWORK-ON-A-CHIP (NOC); ONE-DIMENSIONAL; PARALLEL PROCESSING; PERFORMANCE IMPROVEMENTS; PROCESSING ELEMENTS (PES); SUSTAINED PERFORMANCE;

DATA STORAGE EQUIPMENT;

EID: 47249164386     PISSN: 01903918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICPP.2007.66     Document Type: Conference Paper

References (9)

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9. Tokyo Institute of Technology GSIC. http://www.gsic.titech.ac.jp/index. html.en/.