0.7 v SRAM technology with stress-enhanced Dopant Segregated Schottky (DSS) source/drain transistors for 32 nm node

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2007, Pages 76-77

  Onoda, H ^a   Miyashita, K ^a   Nakayama, T ^a   Kinoshita, T ^a   Nishimura, H ^b   Azuma, A ^c   Yamada, S ^a   Matsuoka, F ^a  

^a System LSI Division I

^b Process and Manufacturing Engineering Center

^c TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BIT LINE (BL); LOW SUPPLY VOLTAGES; ORDERS-OF-MAGNITUDE; SCHOTTKY; SRAM CELLS; VLSI TECHNOLOGIES;

DECISION SUPPORT SYSTEMS; TECHNOLOGY; TRANSISTORS;

STATIC RANDOM ACCESS STORAGE;

EID: 47249153488     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2007.4339733     Document Type: Conference Paper

References (3)

1. T. Kinoshita et al., IEDM (2006), 71
2. A. Kinoshita et al., IEDM (2006), 79
3. C.H. Ko et al., Symp. VLSI Tech (2006), 9