InGaAs and GaAs/InGaAs channel enhancement mode n-MOSFETs with HfO 2 gate oxide and a-Si interface passivation layer

65th DRC Device Research Conference

Volumn , Issue , 2007, Pages 203-204

  Oktyabrsky, Serge ^a   Koveshnikov, Sergei ^b   Tokranov, Vadim ^a   Yakimov, Michael ^a   Kambhampati, Rama ^a   Bakhru, Hassaram ^a   Zhu, Feng ^c   Lee, Jack ^c   Tsai, Wilman ^b  

^a STATE UNIVERSITY OF NEW YORK   (United States)

^b INTEL CORPORATION   (United States)

^c The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 47249143400     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DRC.2007.4373718     Document Type: Conference Paper

References (2)

1. R. Chau, S. Datta, A. Majumdar, " Opportunities and challenges of III-V nanoelectronics for future high-speed, low-power logic applications, "IEEE Compound Semiconductor Integrated Circuit Symposium November 2005.
2. S. Koveshnikov, W. Tsai, I. Ok and J. C. Lee, V. Torkanov, M. Yakimov, and S. Oktyabrsky, "Metal-oxide-semiconductor capacitors on GaAs with high-k gate oxide and amorphous silicon interface passivation layer," Appl. Phys. Lett., vol. 88, pp. 022106-8, 2006.